Abstract: An input output control device between a verification circuit and a semiconductor memory device includes: a first port that receives a read transaction for requesting reading of data in the semiconductor memory device from the verification circuit, and outputs a read response to the verification circuit; a second port that outputs the read transaction to the semiconductor memory device, and receives the read response output from the semiconductor memory device in response to the read transaction; and a buffer device that delays at least one of an output of the read transaction to the semiconductor memory device and an output of the read response to the verification circuit.

Abstract: A memory controller issues a command to a semiconductor memory device in response to an access request from an arithmetic unit to the semiconductor memory device having multiple ranks. The memory controller includes an access request holder, an access request selector, a command generator, a refresh interval counter and a refresh counter. The access request selector calculates a total processing period for each of the ranks, selects multiple access requests as an access request group sent to an access target rank, and determines a processing order of the access requests in the selected access request group. The command generator issues an access command to the access target rank in order, and issues a refresh command to a refresh target rank.

Abstract: A semiconductor memory device includes: a plurality of banks having a data storage unit and an error correction code storage unit; an error correction code generation unit; an error correction unit; a low counter that determines a low address as a refresh target; a bank counter that determines a bank address as an error correction target; and a column counter that determines a column address as the error correction target. The error correction unit performs the error correction process on a data of an error correction target address determined based on the low counter, the bank counter, and the column counter when receiving a refresh command.

Abstract: An access control device, which increases memory access efficiency to data stored in a memory, includes a plurality of groups of the memory, and divides and stores the data in different memory areas of the plurality of groups of the memory, distinguished based on predetermined bits of an access address. The access control device accesses the data stored in the different memory areas simultaneously in the same clock cycle of access to the memory. The predetermined bits of the access address are controlled independently for each of the groups of the memory. The part of the access address other than the predetermined bits controlled independently for each of the groups is common for the plurality of groups. Modes can be selected to access two horizontally or vertically consecutive unit data or data on vertically alternate lines at a time. The data may be image data or pixel data.

Abstract: The memory access system includes first to fourth memories and a memory controller. The memory controller accesses blocks in a first block group respectively stored in the first and second memories by supplying the first and second unique addresses different from each other at a first timing of activating a first chip select signal, and accesses blocks in a second block group respectively stored in the third and fourth memories by supplying the first and second unique addresses different from each other at a second timing of activating a second chip select signal.

Abstract: A memory access control apparatus includes an arbiter and a sub-arbiter receiving and arbitrating access requests from a plurality of memory masters; a memory controller; and a memory having a plurality of banks. When a bank of the memory used by an access request allowed by the arbiter and currently being executed and a bank of the memory to be accessed by an access request by the sub-arbiter are different and the type of access request allowed by the arbiter and currently being executed and the type of memory access to be performed by the sub-arbiter are identical, then it is decided that access efficiency will not decline, memory access by the arbiter is suspended and memory access by the sub-arbiter is allowed to squeeze in (FIG. 1).

Abstract: An access control device which increases memory access efficiency to data stored in a memory according to the present invention comprises a plurality of groups of the memory, divides and stores the data in different memory areas of the plurality of groups of the memory distinguished based on the predetermined bits of an access address to the plurality of groups of the memory, and accesses the data stored in the different memory areas of the plurality of groups of the memory simultaneously in the same clock cycle of access to the memory.

Abstract: A memory access control system is provided which includes a memory master to make a request for access to memory, a memory control section to produce control signals of memories based on access information and a high predicting section to predict whether the next access to each bank in memory is obtained to a same page (hit is found) wherein the memory control section, when the hit predicting section predicts that a hit is found, terminates its routine without closing the bank being presently accessed at time of completion of present access operations and, when the hit predicting section predicts that a miss is found, closes a bank being presently accessed and terminates its routine.

Abstract: A memory compression and expansion section (11 of FIG. 1) applies compression to a decoded image, and the result is stored in a frame memory. Based on an occupied content of the frame memory (FIG. 1, 106), in case that the number of coded bits for a single or a plurality of memory compression processing blocks or for every control unit of memory compression processing exceeds the number of bits of a memory access unit or is lacking, a memory access width control section (110 of FIG. 1) applies control to a quantizer control section (109 of FIG. 1) so that the number of coded bits is conformed to be equal to or less than the number of bits of memory access unit.

Abstract: Probabilities of the changeovers of access pages in the same bank and the changes of types of accesses, for instance the change from read to write or from write to read, are reduced and thereby data transmission performance is improved. If respective memory masters want to acquire the memory use right, they assert request signals and, at the same time, fix address signals and read/write signals. A memory arbitration circuit determines the priority order over the memory use right for the respective memory masters, and asserts an acknowledgement signal for a memory master having the highest priority.

Abstract: A memory access control system is provided which is made up of a memory master to make a request for access to memory, a memory control section to produce control signals of memories based on access information and a hit predicting section to predict whether next access to each bank in memory is gotten to a same page (page hit is found) wherein the memory control section, when the hit predicting section predicts that a page hit is found, terminates its routine without closing the bank being presently accessed at time of completion of present access operations and, when the hit predicting section predicts that a miss hit is found, closes a bank being presently accessed and terminates its routine.

Abstract: Probabilities of the changeovers of access pages in the same bank and the changes of types of accesses, for instance the change from read to write or from write to read, are reduced and thereby data transmission performance is improved.

Abstract: On storing two-dimensional arrangement data into a memory (1) having banks, 2n in number, each of which is individually assigned with a bank number B and includes row addresses identified by row address numbers A, an address converter (3) calculates, in response to a coordinate (X, Y) representing a particular data element of the data elements of the two-dimensional arrangement data, the bank number B of a particular bank of the banks where the particular data element is to be memorized. The bank number B is given by: B={Y×(2n×m+k)+X}mod 2n, where m is a positive integer, where k is a positive integer smaller than 2n and other than 1, and where mod is an operator for calculating a remainder. The address converter also calculates the row address number A of a particular address of the row addresses of the particular bank where the particular data element is to be memorized.

Abstract: A graphics display unit is equipped with a frame buffer, an image drawing unit, and a display unit. This frame buffer is arranged by a normal data storage region for directly storing a display content as pixel data, and a compression data storage region for compressing the pixel data as compression data. The display unit is equipped with a flag buffer for storing information indicating as to whether the storage content of said compression data storage region is valid, or invalid, and a compressing unit, and an expanding unit. When the display content is read, while the control unit refers to the flag buffer, if the compression data of the compression region is valid, then the compression data is read from the compression data region and this read compression data is restored as the original data by the expanding unit so as to display the original image. If the compression data is invalid, then the normal data is read from the normal data storage region to be displayed.

Abstract: To provide a video display device which can display video data on a display screen even when there is no or insufficient idle space in a frame buffer (41), a video display device according to the invention of a graphics accelerator (40) comprises a DMA controller (44) for reading out video data prepared in a main memory (50), and video data processing section (45) for processing the video data to be displayed on a display device (60).

Abstract: A single frame buffer is used in displaying on a display both an image from a first-type image source specified by a red-green-blue (RGB) value and an image from a second-type image source specified by an index value for a look-up table. A data-type buffer stores a data-type indicating whether each value stored in the frame buffer is the RGB value or the index value corresponding to each pixel on the display. A buffer writer may compress the RGB value. A buffer reader may decompress the RGB value from the compressed RGB value.