Patents by Inventor Tetsushi Tanizaki
Tetsushi Tanizaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7505352Abstract: In a parallel operational processing device having an operational processing unit arranged between memory blocks each having a plurality of memory cells arranged in rows and columns, the respective columns of each memory block are alternately connected to the operational processing units on the opposite sides of the memory block. By selecting one word line in one memory block, data can be transferred to two operational processing units. The number of the word lines selected per one operational processing unit is reduced, and power consumption is reduced. The bit operation units and sense amplifiers/write drivers of the operational processing units have arrangement pitch conditions mitigated and are reduced in number, and an isolation region between the memory blocks is not required and the layout area is reduced. Thus, the parallel operational processing device with a layout area and the power consumption reduced, can achieve a fast operation.Type: GrantFiled: January 26, 2007Date of Patent: March 17, 2009Assignee: Renesas Technology Corp.Inventors: Takayuki Gyoten, Katsumi Dosaka, Hideyuki Noda, Tetsushi Tanizaki
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Publication number: 20070180006Abstract: In a parallel operational processing device having an operational processing unit arranged between memory blocks each having a plurality of memory cells arranged in rows and columns, the respective columns of each memory block are alternately connected to the operational processing units on the opposite sides of the memory block. By selecting one word line in one memory block, data can be transferred to two operational processing units. The number of the word lines selected per one operational processing unit is reduced, and power consumption is reduced. The bit operation units and sense amplifiers/write drivers of the operational processing units have arrangement pitch conditions mitigated and are reduced in number, and an isolation region between the memory blocks is not required and the layout area is reduced. Thus, the parallel operational processing device with a layout area and the power consumption reduced, can achieve a fast operation.Type: ApplicationFiled: January 26, 2007Publication date: August 2, 2007Applicant: Renesas Technology Corp.Inventors: Takayuki Gyoten, Katsumi Dosaka, Hideyuki Noda, Tetsushi Tanizaki
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Patent number: 7032141Abstract: A test interface circuit, which has a simple pattern generator mounted on a semiconductor device having a mounted memory, consists of a command analysis section which analyses a command of three bits received from a tester, outputs an analysis result to a memory core and controls an operation of the memory core, and an address counter which counts addresses and outputs the addresses to the memory core in accordance with a counter control instruction of two bits received from the tester. It is, therefore, possible to make a circuit for testing the memory core small in scale and to decrease the number of pins for testing the memory core, so that it is possible to use an inexpensive tester and to reduce cost required to test the memory core.Type: GrantFiled: July 19, 2002Date of Patent: April 18, 2006Assignee: Renesas Technology Corp.Inventor: Tetsushi Tanizaki
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Patent number: 7007215Abstract: A test signal applied to an embedded memory is changed in synchronization with a test clock signal, set to an invalidated state by an asynchronous control signal asynchronous to the test clock signal and then is applied to a memory. The memory takes in a received signal in synchronization with a memory clock signal. An invalid data generating circuit modifies the test signal in accordance with the asynchronous control signal and generates a test signal and to apply the test signal to the memory. A period of an invalid state of the modified test signal can be adjusted and therefore, by monitoring a changing timing of the asynchronous control signal PTX with an external tester, setup and hold times of a signal for the memory can be measured. Setup and hold times and an access time for an embedded memory can be correctly measured.Type: GrantFiled: June 18, 2002Date of Patent: February 28, 2006Assignee: Renesas Technology Corp.Inventors: Mitsuya Kinoshita, Tetsushi Tanizaki, Masaru Haraguchi, Katsumi Dosaka
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Patent number: 6993696Abstract: A semiconductor memory device with a built-in self test circuit includes a semiconductor substrate, a memory cell array formed on the semiconductor substrate, an input buffer provided on the semiconductor substrate to receive externally applied data, a test circuit coupled to the memory cell array and the input buffer on the semiconductor substrate to store a program received through the input buffer to generate test data of the memory cell array according to the stored program to carry out testing of the memory cell array, and a select circuit selectively applying to the memory cell array test data applied from the test circuit and data applied from the input buffer depending upon a test operation and a normal operation.Type: GrantFiled: November 15, 2000Date of Patent: January 31, 2006Assignees: Renesas Technology Corp., Ryoden Semiconductor System Engineering CorporationInventors: Tetsushi Tanizaki, Kazushi Sugiura, Masami Nakajima
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Patent number: 6962827Abstract: A plurality of semiconductor integrated circuits and a plurality of TEG circuits are aligned and provided on a substrate. In the TEG circuit, a built-in test circuit is provided in a region which faces a semiconductor integrated circuit across a dicing line region. The built-in test circuit and the semiconductor integrated circuit are connected by an interconnection which is provided on the dicing line region. The interconnection is cut for isolation into chips.Type: GrantFiled: August 14, 2003Date of Patent: November 8, 2005Assignee: Renesas Technology Corp.Inventors: Katsuya Furue, Shigeru Kikuda, Kiyohiro Furutani, Tetsushi Tanizaki, Shigehiro Kuge, Takashi Kono
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Publication number: 20040250165Abstract: A boundary scan cell in a semiconductor memory device (memory core) is provided corresponding to each terminal for performing a boundary scan test. A test controller and a read/write control circuit cause the boundary scan cell to latch input write data in a late write operation, until a next write cycle of the write cycle at which the write data was input from the terminal.Type: ApplicationFiled: August 28, 2003Publication date: December 9, 2004Applicant: RENESAS TECHNOLOGY CORP.Inventor: Tetsushi Tanizaki
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Patent number: 6782498Abstract: In the semiconductor memory device, a control circuit generates various commands for a memory cell array according to an internal command control signal and an internal address signal output from an input switching circuit for switching an input source of the command control signals and the address signal between an external terminal and a BIST circuit. In the BIST mode, the input switching circuit cuts the signal input from the external terminal and generates the internal command control signal and the internal address signal according to an output signal from the BIST circuit. Transition to the BIST mode and return to the normal operation mode are indicated by a combination of signals supplied to the external terminal. Therefore, an interface between a built in BIST circuit and other internal circuits can be secured without an addition of a special interface specification.Type: GrantFiled: January 11, 2001Date of Patent: August 24, 2004Assignee: Renesas Technology Corp.Inventors: Tetsushi Tanizaki, Takeshi Hamamoto
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Patent number: 6779139Abstract: A semiconductor memory device includes: a determination section; an expected value control section; and an accumulation section. The determination section determines coincidence/non-coincidence between input data and an expected value. The expected value control section catches a read expected value in a read operation only. The accumulation section catches a determination result according to an accumulation-transmission signal. When the accumulation-transmission signal is in a transmission state, a determination result is caught, while when the accumulation-transmission signal enters an accumulation state, the next determination result is caught in a case of coincidence determination and once a non-coincidence determination result is caught, thereafter the non-coincidence determination result continues to be held.Type: GrantFiled: May 1, 2001Date of Patent: August 17, 2004Assignee: Renesas Technology Corp.Inventors: Masaru Haraguchi, Katsumi Dosaka, Tetsushi Tanizaki
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Patent number: 6762967Abstract: A semiconductor memory device includes a command decoder receiving an external signal and issuing a command, a clock buffer receiving an external clock, gates and a refresh counter. When a test signal is at L-level, an auto-refresh signal is issued in accordance with the output of the command decoder. When the test signal is at H-level, the auto-refresh signal is issued in accordance with the output (external clock) of the clock buffer. Thereby, the test can be performed with a good timing accuracy even by a low-speed tester.Type: GrantFiled: May 23, 2003Date of Patent: July 13, 2004Assignee: Renesas Technology Corp.Inventors: Tetsushi Tanizaki, Katsumi Dosaka, Mikio Asakura
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Patent number: 6704229Abstract: In a test circuit for testing an eDRAM provided with a write mask function, eight internal expected values are generated based on a prescribed read data signal among read data signals of one unit of write mask (i.e., eight). Determination is performed as to whether the eight read data signals and the eight internal expected values respectively match or not, and when they match, the eight memory cells are determined to be normal. Thus, a multi-bit test can be performed even when a test pattern is written using a write mask function.Type: GrantFiled: April 16, 2002Date of Patent: March 9, 2004Assignee: Renesas Technology Corp.Inventors: Masaru Haraguchi, Tetsushi Tanizaki
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Publication number: 20030218928Abstract: A semiconductor memory device includes a command decoder receiving an external signal and issuing a command, a clock buffer receiving an external clock, gates and a refresh counter. When a test signal is at L-level, an auto-refresh signal is issued in accordance with the output of the command decoder. When the test signal is at H-level, the auto-refresh signal is issued in accordance with the output (external clock) of the clock buffer. Thereby, the test can be performed with a good timing accuracy even by a low-speed tester.Type: ApplicationFiled: May 23, 2003Publication date: November 27, 2003Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Tetsushi Tanizaki, Katsumi Dosaka, Mikio Asakura
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Patent number: 6614713Abstract: A semiconductor memory device includes a command decoder receiving an external signal and issuing a command, a clock buffer receiving an external clock, gates and a refresh counter. When a test signal is at L-level, an auto-refresh signal is issued in accordance with the output of the command decoder. When the test signal is at H-level, the auto-refresh signal is issued in accordance with the output (external clock) of the clock buffer. Thereby, the test can be performed with a good timing accuracy even by a low-speed tester.Type: GrantFiled: August 7, 2001Date of Patent: September 2, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Tetsushi Tanizaki, Katsumi Dosaka, Mikio Asakura
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Publication number: 20030145261Abstract: A TIC, which has a simple PG mounted on a semiconductor device having a mounted memory, consists of a command analysis section which analyses a command of three bits received from a tester, outputs an analysis result to a memory core and controls an operation of the memory core, and an address counter which counts addresses and outputs the addresses to the memory core in accordance with a counter control instruction of two bits received from the tester. It is, therefore, possible to make a circuit for testing the memory core small in scale and to decrease the number of pins for testing the memory core, so that it is possible to use an inexpensive tester and to reduce cost required to test the memory core.Type: ApplicationFiled: July 19, 2002Publication date: July 31, 2003Applicant: Mitsubishi Denki Kabushiki KaishaInventor: Tetsushi Tanizaki
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Publication number: 20030043663Abstract: In a test circuit for testing an eDRAM provided with a write mask function, eight internal expected values are generated based on a prescribed read data signal among read data signals of one unit of write mask (i.e., eight). Determination is performed as to whether the eight read data signals and the eight internal expected values respectively match or not, and when they match, the eight memory cells are determined to be normal. Thus, a multi-bit test can be performed even when a test pattern is written using a write mask function.Type: ApplicationFiled: April 16, 2002Publication date: March 6, 2003Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Masaru Haraguchi, Tetsushi Tanizaki
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Publication number: 20030018939Abstract: A test signal applied to an embedded memory is changed in synchronization with a test clock signal, set to an invalidated state by an asynchronous control signal asynchronous to the test clock signal and then is applied to a memory. The memory takes in a received signal in synchronization with a memory clock signal. An invalid data generating circuit modifies the test signal in accordance with the asynchronous control signal and generates a test signal and to apply the test signal to the memory. A period of an invalid state of the modified test signal can be adjusted and therefore, by monitoring a changing timing of the asynchronous control signal PTX with an external tester, setup and hold times of a signal for the memory can be measured. Setup and hold times and an access time for an embedded memory can be correctly measured.Type: ApplicationFiled: June 18, 2002Publication date: January 23, 2003Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Mitsuya Kinoshita, Tetsushi Tanizaki, Masaru Haraguchi, Katsumi Dosaka
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Patent number: 6496429Abstract: A spare data terminal for inputting/outputting spare memory cell data to the outside of a semiconductor memory device and a terminal for inputting/outputting normal memory cell data are provided separately from each other. In a test mode, the data terminals are coupled in parallel to internal data line pairs and, simultaneously, a spare data line pair is coupled to the spare data terminal. Thus, test time for detecting a defective bit in the semiconductor memory device can be shortened.Type: GrantFiled: November 19, 2001Date of Patent: December 17, 2002Assignees: Mitsubishi Denki Kabushiki Kaisha, Mitsubishi Electric Engineering Company LimitedInventors: Yasumitsu Murai, Tetsushi Tanizaki, Masaru Haraguchi
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Publication number: 20020131307Abstract: A spare data terminal for inputting/outputting spare memory cell data to the outside of a semiconductor memory device and a terminal for inputting/outputting normal memory cell data are provided separately from each other. In a test mode, the data terminals are coupled in parallel to internal data line pairs and, simultaneously, a spare data line pair is coupled to the spare data terminal. Thus, test time for detecting a defective bit in the semiconductor memory device can be shortened.Type: ApplicationFiled: November 19, 2001Publication date: September 19, 2002Applicant: Mitsubishi Denki Kabushiki Kaisha,Inventors: Yasumitsu Murai, Tetsushi Tanizaki, Masaru Haraguchi
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Publication number: 20020056061Abstract: A semiconductor memory device includes: a determination section; an expected value control section; and an accumulation section. The determination section determines coincidence/non-coincidence between input data and an expected value. The expected value control section catches a read expected value in a read operation only. The accumulation section catches a determination result according to an accumulation-transmission signal. When the accumulation-transmission signal is in a transmission state, a determination result is caught, while when the accumulation-transmission signal enters an accumulation state, the next determination result is caught in a case of coincidence determination and once a non-coincidence determination result is caught, thereafter the non-coincidence determination result continues to be held.Type: ApplicationFiled: May 1, 2001Publication date: May 9, 2002Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Masaru Haraguchi, Katsumi Dosaka, Tetsushi Tanizaki
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Patent number: 6337506Abstract: A power supply circuit and an oscillation circuit or the like of noise generation sources are concentrated, and the periphery thereof is surrounded by a guard ring. Guard ring is provided to have bonding pads at least partially thereon. Guard ring is effectively provided utilizing the region below bonding pads, so that effective noise reduction is achieved while preventing increase in chip area.Type: GrantFiled: July 16, 1998Date of Patent: January 8, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Fukashi Morishita, Teruhiko Amano, Kazutami Arimoto, Tetsushi Tanizaki, Takeshi Fujino, Takahiro Tsuruda, Mitsuya Kinoshita, Mako Kobayashi