Patents by Inventor Tetsuya Izu

Tetsuya Izu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11451403
    Abstract: A verification method implemented by a first system including a plurality of computers, the method includes: calculating a first hash value for an original document; calculating a second hash value for an original document by using the first hash value; calculating a first modified version's first hash value for the first modified version document; calculating a first modified version's second hash value that is a hash value obtained by combining the first modified version's first hash value and the original document's second hash value; in response to a second modified version document obtained by modifying the first modified version document, calculating a second modified version's first hash value for the second modified version document; and calculating a second modified version's second hash value that is a hash value obtained by combining the second modified version's first hash value and the first modified version's second hash value.
    Type: Grant
    Filed: December 22, 2020
    Date of Patent: September 20, 2022
    Assignee: FUJITSU LIMITED
    Inventors: Rikuhiro Kojima, Dai Yamamoto, Tetsuya Izu
  • Publication number: 20220222042
    Abstract: A computer-implemented method includes: acquiring an evaluation function represented by a product of high-degree polynomials; generating a quadratic polynomial equivalent to the evaluation function by applying a degree reduction one or more times to each of the high-degree polynomials that represent the acquired evaluation function without expanding the evaluation function; and performing annealing calculation on the generated quadratic polynomial.
    Type: Application
    Filed: November 23, 2021
    Publication date: July 14, 2022
    Applicant: FUJITSU LIMITED
    Inventors: Jumpei YAMAGUCHI, Tetsuya IZU, Takashige AKIYAMA
  • Publication number: 20210226801
    Abstract: A verification method implemented by a first system including a plurality of computers, the method includes: calculating a first hash value for an original document; calculating a second hash value for an original document by using the first hash value; calculating a first modified version's first hash value for the first modified version document; calculating a first modified version's second hash value that is a hash value obtained by combining the first modified version's first hash value and the original document's second hash value; in response to a second modified version document obtained by modifying the first modified version document, calculating a second modified version's first hash value for the second modified version document; and calculating a second modified version's second hash value that is a hash value obtained by combining the second modified version's first hash value and the first modified version's second hash value.
    Type: Application
    Filed: December 22, 2020
    Publication date: July 22, 2021
    Applicant: FUJITSU LIMITED
    Inventors: Rikuhiro Kojima, Dai YAMAMOTO, Tetsuya Izu
  • Patent number: 9772819
    Abstract: An apparatus for generating physical random numbers includes a physical random number generator configured to generate physical random numbers, a test unit configured to perform a test process to check randomness of the physical random numbers, a minimum entropy estimating unit configured to estimate a minimum entropy based on statistical information generated as a byproduct of the test process, an entropy compressing unit configured to perform an entropy compression process using the physical random numbers as an input, and an entropy control unit configured to control based on the minimum entropy a number of bits of the physical random numbers input into the entropy compression process performed by the entropy compressing unit.
    Type: Grant
    Filed: November 17, 2014
    Date of Patent: September 26, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Hirotaka Kokubo, Dai Yamamoto, Masahiko Takenaka, Kazuyoshi Furukawa, Tetsuya Izu
  • Patent number: 9760717
    Abstract: A communication device includes a memory and a processor coupled to the memory and configured to, when a first vibration is detected in the communication device, set a certain state that protects information stored in the memory, and cancel the certain state based on receiving from another communication device a notification indicating that the other communication device detected a second vibration.
    Type: Grant
    Filed: August 14, 2014
    Date of Patent: September 12, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Yumi Sakemi, Tetsuya Izu, Yoshinobu Shimokawa, Tadashige Iwao
  • Patent number: 9712499
    Abstract: A cryptographic processing apparatus that holds a first key, and receives authentication object data upon authentication includes a communication unit and a computing unit. The communication unit communicates with a calculation apparatus and a determination apparatus. In the calculation apparatus, encrypted registration data obtained by encrypting registration data twice, once with the first key and once with a second key, is registered. The registration data is data against which the authentication object data is verified. The determination apparatus uses the second key upon the authentication. When registering the encrypted registration data in the calculation apparatus, the computing unit generates a key different from the first key, generates encrypted data by encrypting the registration data twice, once with the first key and once with the different key, transmits the different key to the determination apparatus, and the encrypted data to the calculation apparatus, through the communication unit.
    Type: Grant
    Filed: March 25, 2015
    Date of Patent: July 18, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Yumi Sakemi, Tetsuya Izu, Masahiko Takenaka
  • Patent number: 9614822
    Abstract: A node device in a network system includes a memory and a processor. The node device is identified with a first value related to a first element and a second value related to a second element. The memory stores a first key corresponding to the first value, a second key corresponding to the second value, first information on a first range of values and second information on a second range of values, at least one of the first key and the second key being shared by at least three or more node devices in the network system. The processor communicates with one of at least three or more node devices indicated by the first value related to the first element and the second value related to the second element using one of the first key and the second key.
    Type: Grant
    Filed: January 20, 2015
    Date of Patent: April 4, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Yumi Sakemi, Tetsuya Izu
  • Patent number: 9510216
    Abstract: A node device includes: a processor configured to: receive a first packet that is transferred from a source to a destination via at least one node device including the node device, the first packet including a counter value regarding a number of transfers of the first packet, and first coding information according to a first key information and contents of the first packet, determine whether to conduct a verifying process on the first packet based on the counter value, verify the first coding information is same as a second coding information, the second coding information being generated according to the contents of the first packet and a second key information stored in the memory, change the counter value in the first packet to an initial value, and transmit the first packet including a changed counter value to the destination or any one of the plurality of node devices.
    Type: Grant
    Filed: May 12, 2014
    Date of Patent: November 29, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Tetsuya Izu, Yumi Sakemi, Kazuyoshi Furukawa, Hisashi Kojima, Masahiko Takenaka
  • Patent number: 9489501
    Abstract: An authentication method executed by a computer includes: receiving input data which is a target of authentication; specifying registration data, from among a plurality of registration data stored in a storage device, having a second feature value within a threshold value relative to a first feature value of the input data, the first feature value representing a distance between the input data and a reference, the second feature value representing another distance between the registration data and the reference, and the threshold value being used when a determination as to whether the authentication has been successfully performed; and executing a process of comparing the registration data with the input data.
    Type: Grant
    Filed: September 10, 2014
    Date of Patent: November 8, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Yumi Sakemi, Tetsuya Izu
  • Patent number: 9386017
    Abstract: An authentication device includes: a memory; and a processor coupled to the memory and configured to: when a registration request including authentication information to be used during authentication is received from a terminal device, generate registration information using the authentication information and key information and store the registration information in the memory, and when an authentication request including input information to be handled as the target of the authentication is received from the terminal device, generate a result of the authentication based on the input information, the registration information, and the key information, and transmit the result of the authentication to the terminal device.
    Type: Grant
    Filed: May 6, 2014
    Date of Patent: July 5, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Yumi Sakemi, Tetsuya Izu, Masahiko Takenaka, Masaya Yasuda
  • Patent number: 9319923
    Abstract: A node in an ad-hoc network includes a memory unit storing a concatenated counter value including an erasure counter value and a transmission counter value for the node; and a processor configured to: add one to the transmission counter value, when the node transmits data to another node in the ad-hoc network; transmit to the other node, the data and the updated concatenated counter value; detect erasure of the concatenated counter value in the memory unit; distribute in the ad-hoc network and upon detecting the erasure, an acquisition request for the erasure counter value; receive the erasure counter value consequent to the acquisition request; generate the concatenated counter value to include the received erasure counter value plus one and the transmission counter value after the erasure and indicating the number of transmissions as zero due to the erasure; and archive to the memory unit, the generated concatenated counter value.
    Type: Grant
    Filed: June 5, 2014
    Date of Patent: April 19, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Tetsuya Izu, Masahiko Takenaka, Hisashi Kojima, Kazuyoshi Furukawa
  • Patent number: 9203800
    Abstract: A communication method executed by a node in an ad hoc network having multiple nodes, includes receiving from a neighboring node of the node in the ad hoc network, a first packet that includes a sender address of the neighboring node and a first packet transmission count of packet transmissions from the neighboring node; extracting the first packet transmission count from the first packet; receiving from the neighboring node and after reception of the first packet, a second packet that includes the sender address of the neighboring node and a second packet transmission count of packet transmissions from the neighboring node; extracting the second packet transmission count from the second packet; determining whether the second packet is an invalid packet, based on the first packet transmission count and the second packet transmission count; and discarding the second packet upon determining the second packet to be an invalid packet.
    Type: Grant
    Filed: July 29, 2013
    Date of Patent: December 1, 2015
    Assignee: FUJITSU LIMITED
    Inventors: Tetsuya Izu, Masahiko Takenaka, Kazuyoshi Furukawa, Hisashi Kojima
  • Publication number: 20150281187
    Abstract: A method for a key transmission includes: transmitting, by a user terminal, a first public key of the user terminal, an electronic signature for the first public key, and an electronic certificate signing the first public key to a first information processing apparatus via a communication apparatus that communicates with the first information processing apparatus, a second information processing apparatus, and the user terminal; and transmitting, by the first information processing apparatus, the first public key to the second information processing apparatus via a route that does not link to the communication apparatus when the first information processing apparatus determines that the first public key is authentic using the electronic signature and the electronic certificate.
    Type: Application
    Filed: March 6, 2015
    Publication date: October 1, 2015
    Inventors: Takao Ogura, Tetsuya Izu
  • Publication number: 20150281188
    Abstract: A cryptographic processing apparatus that holds a first key, and receives authentication object data upon authentication includes a communication unit and a computing unit. The communication unit communicates with a calculation apparatus and a determination apparatus. In the calculation apparatus, encrypted registration data obtained by encrypting registration data twice, once with the first key and once with a second key, is registered. The registration data is data against which the authentication object data is verified. The determination apparatus uses the second key upon the authentication. When registering the encrypted registration data in the calculation apparatus, the computing unit generates a key different from the first key, generates encrypted data by encrypting the registration data twice, once with the first key and once with the different key, transmits the different key to the determination apparatus, and the encrypted data to the calculation apparatus, through the communication unit.
    Type: Application
    Filed: March 25, 2015
    Publication date: October 1, 2015
    Inventors: Yumi SAKEMI, Tetsuya IZU, Masahiko TAKENAKA
  • Publication number: 20150188704
    Abstract: A first random number receiver receives a first encrypted random number from a data communication apparatus. A second random number transmitter decrypts the first encrypted random number using a first private key to obtain a first random number, encrypts a second random number into a second encrypted random number using a second public key, and transmits it to the data communication apparatus. A hash value receiver receives a first hash value from the data communication apparatus. A session key generator generates a second hash value from the first random number decrypted with the first private key and the second random number, and generates a session key based on the first random number and the second random number when the first hash value is equal to the second hash value. In such key sharing communication, a data communication apparatus and another data communication apparatus achieve three-way handshake.
    Type: Application
    Filed: December 24, 2014
    Publication date: July 2, 2015
    Inventors: Masahiko TAKENAKA, Tetsuya IZU, Yumi SAKEMI
  • Patent number: 9071420
    Abstract: An information processing apparatus includes a processor configured to identify a data length that is longer than a data length of plain text data and that is a multiple of a predetermined block length; calculate a data length difference of the data length of the plain text and the data length; generate a first code that indicates the calculated data length difference; generate a second code that is calculated from the plain text data and is of a data length that is within a remaining data length acquired by subtracting a data length of the generated first code from the data length difference; create padding that includes the generated second code, has the first code at an end, and is of a length equivalent to the data length difference; concatenate the created padding to an end of the plain text data to generate concatenated data; and output the concatenated data.
    Type: Grant
    Filed: September 20, 2013
    Date of Patent: June 30, 2015
    Assignee: FUJITSU LIMITED
    Inventors: Jun Yajima, Tetsuya Izu, Masahiko Takenaka
  • Publication number: 20150163053
    Abstract: A relay apparatus includes: a memory; and one or more processors coupled to the memory and configured to: generate second encrypted data by performing a second encryption process using a second key shared with a providing destination apparatus in a second network on first encrypted data which is generated by a node apparatus in a first network performing a first encryption process using a first key on data, generate decrypted data by performing a decryption process using the first key on the second encrypted data, and transmit the decrypted data to the providing destination apparatus.
    Type: Application
    Filed: February 18, 2015
    Publication date: June 11, 2015
    Applicant: FUJITSU LIMITED
    Inventors: Tetsuya Izu, Masahiko Takenaka
  • Publication number: 20150149519
    Abstract: An apparatus for generating physical random numbers includes a physical random number generator configured to generate physical random numbers, a test unit configured to perform a test process to check randomness of the physical random numbers, a minimum entropy estimating unit configured to estimate a minimum entropy based on statistical information generated as a byproduct of the test process, an entropy compressing unit configured to perform an entropy compression process using the physical random numbers as an input, and an entropy control unit configured to control based on the minimum entropy a number of bits of the physical random numbers input into the entropy compression process performed by the entropy compressing unit.
    Type: Application
    Filed: November 17, 2014
    Publication date: May 28, 2015
    Inventors: Hirotaka KOKUBO, Dai YAMAMOTO, Masahiko TAKENAKA, Kazuyoshi FURUKAWA, Tetsuya IZU
  • Publication number: 20150134963
    Abstract: A node device in a network system includes a memory and a processor. The node device is identified with a first value related to a first element and a second value related to a second element. The processor identifies a relay node device capable of cryptographic communications with the node device based on status information in the memory when a first common key is not shared by the node device and a first sharing destination node device not identified with the first value related to the first element and the second value related to the second element, and transmit to the relay node device a request for transfer of the first common key to the first sharing destination node device.
    Type: Application
    Filed: January 20, 2015
    Publication date: May 14, 2015
    Applicant: FUJITSU LIMITED
    Inventors: Tetsuya IZU, Yumi SAKEMI
  • Publication number: 20150134964
    Abstract: A node device in a network system includes a memory and a processor. The node device is identified with a first value related to a first element and a second value related to a second element. The memory stores a first key corresponding to the first value, a second key corresponding to the second value, first information on a first range of values and second information on a second range of values, at least one of the first key and the second key being shared by at least three or more node devices in the network system. The processor communicates with one of at least three or more node devices indicated by the first value related to the first element and the second value related to the second element using one of the first key and the second key.
    Type: Application
    Filed: January 20, 2015
    Publication date: May 14, 2015
    Applicant: FUJITSU LIMITED
    Inventors: Yumi SAKEMI, Tetsuya Izu