Patents by Inventor Tetsuya Kagami
Tetsuya Kagami has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11454664Abstract: A testing system includes: an inspection module including a plurality of levels of inspection chambers in each of which a tester part having a tester configured to perform an electrical inspection of an inspection object and a probe card is accommodated; an aligner module configured to align the inspection object with the tester part; an alignment area in which the aligner module is accommodated; and a loader part configured to load the inspection object into the alignment area and unload the inspection object out of the aligner module, wherein the inspection module is located adjacent to the alignment area.Type: GrantFiled: April 16, 2018Date of Patent: September 27, 2022Assignee: TOKYO ELECTRON LIMITEDInventors: Kentaro Konishi, Jun Fujihara, Hiroki Shikagawa, Hiroshi Yamada, Yukinori Murata, Katsuaki Sugiyama, Shin Uchida, Tetsuya Kagami, Hiroaki Hayashi, Rika Ozawa, Takanori Hyakudomi, Xingjun Jiang, Kenichi Narikawa, Tomoya Endo
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Patent number: 11187747Abstract: An inspection system includes a prober, a tester and a malfunction analysis/prediction unit. The prober has a stage holding a substrate having multiple devices formed thereon, a transport unit that transfers the substrate to the stage, and a probe card that brings a plurality of probes into contact with electrodes of the multiple devices on the substrate. A tester applies electrical signals to the multiple devices on the substrate through the probe card and inspects electrical characteristics of the multiple devices. The malfunction analysis/prediction unit, when a malfunction or a sign indicating a stage leading to the malfunction has occurred during an inspection, analyzes history information of the prober and tester related to the malfunction to determine or predict a location of the malfunction.Type: GrantFiled: January 30, 2018Date of Patent: November 30, 2021Assignee: TOKYO ELECTRON LIMITEDInventor: Tetsuya Kagami
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Publication number: 20210364550Abstract: This testing system comprises a prober, a tester, a prober control unit for controlling the prober, and a tester control unit for controlling the tester, wherein the tester control unit causes the tester to execute a test which is composed of a plurality of parts on a device to be tested formed on a test body in addition to acquiring an estimated test ending time when the test has reached a predetermined stage, and sends a control signal to the prober control unit so as to transfer the test body into a testing chamber housing the tester before the estimated test ending time.Type: ApplicationFiled: July 27, 2018Publication date: November 25, 2021Inventor: Tetsuya KAGAMI
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Publication number: 20210333319Abstract: A testing system includes: an inspection module including a plurality of levels of inspection chambers in each of which a tester part having a tester configured to perform an electrical inspection of an inspection object and a probe card is accommodated; an aligner module configured to align the inspection object with the tester part; an alignment area in which the aligner module is accommodated; and a loader part configured to load the inspection object into the alignment area and unload the inspection object out of the aligner module, wherein the inspection module is located adjacent to the alignment area.Type: ApplicationFiled: April 16, 2018Publication date: October 28, 2021Inventors: Kentaro KONISHI, Jun FUJIHARA, Hiroki SHIKAGAWA, Hiroshi YAMADA, Yukinori MURATA, Katsuaki SUGIYAMA, Shin UCHIDA, Tetsuya KAGAMI, Hiroaki HAYASHI, Rika OZAWA, Takanori HYAKUDOMI, Xingjun JIANG, Kenichi NARIKAWA, Tomoya ENDO
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Patent number: 11009544Abstract: An inspection system is provided with a prober and a tester. The tester includes a plurality of tester module boards on which a plurality of LSIs respectively corresponding to a plurality of devices under test (DUT) are mounted; a display unit which displays a wafer map indicating inspection results of the plurality of DUTs and/or self-diagnosis results of the tester; and a tester control unit which includes a wafer map drawing application for drawing the wafer map displayed on the display unit. The wafer map drawing application causes the inspection results and/or the self-diagnosis results to be displayed for each of the plurality of DUTs in a stepwise manner. In the wafer map, the plurality of DUTs are respectively linked to correspond to the plurality of LSIs mounted on the plurality of tester module boards.Type: GrantFiled: February 8, 2018Date of Patent: May 18, 2021Assignee: TOKYO ELECTRON LIMITEDInventors: Shin Uchida, Tetsuya Kagami
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Patent number: 10871516Abstract: An inspection system includes a plurality of prober units each configured to bring probes of a probe card into contact with devices formed on a substrate on a stage, and a tester configured to apply electrical signals to the devices on the substrate through the probe card to inspect electrical characteristics of the devices. The plurality of prober units are arranged such that a plurality of units each of which has the prober units stacked in multiple stages are arranged in multiple rows in a horizontal direction, and at least one test unit constituting a main part of the tester is arranged to a side of a predetermined prober unit among the plurality of prober units.Type: GrantFiled: February 1, 2018Date of Patent: December 22, 2020Assignee: TOKYO ELECTRON LIMITEDInventor: Tetsuya Kagami
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Publication number: 20200174073Abstract: The present invention has a first step for inputting an inspection signal having a predetermined pattern simultaneously to a plurality of devices connected in parallel to a tester and starting inspection having a predetermined pattern, a second step for determining whether a non-passing device is included in the predetermined pattern, a third step for sequentially executing a predetermined pattern and determining passing/non-passing (PASS/FAIL) status for each of the plurality of devices when it is determined in the second step that a non-passing device is included, and a fourth step for excluding a device determined as non-passing in the third step, subsequent inspection being performed for the devices other than the excluded device.Type: ApplicationFiled: March 1, 2018Publication date: June 4, 2020Inventor: Tetsuya KAGAMI
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Publication number: 20200064398Abstract: An inspection system is provided with a prober and a tester. The tester includes a plurality of tester module boards on which a plurality of LSIs respectively corresponding to a plurality of devices under test (DUT) are mounted; a display unit which displays a wafer map indicating inspection results of the plurality of DUTs and/or self-diagnosis results of the tester; and a tester control unit which includes a wafer map drawing application for drawing the wafer map displayed on the display unit. The wafer map drawing application causes the inspection results and/or the self-diagnosis results to be displayed for each of the plurality of DUTs in a stepwise manner. In the wafer map, the plurality of DUTs are respectively linked to correspond to the plurality of LSIs mounted on the plurality of tester module boards.Type: ApplicationFiled: February 8, 2018Publication date: February 27, 2020Inventors: Shin UCHIDA, Tetsuya KAGAMI
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Publication number: 20200011927Abstract: An inspection system includes a prober, a tester and a malfunction analysis/prediction unit. The prober has a stage holding a substrate having multiple devices formed thereon, a transport unit that transfers the substrate to the stage, and a probe card that brings a plurality of probes into contact with electrodes of the multiple devices on the substrate. A tester applies electrical signals to the multiple devices on the substrate through the probe card and inspects electrical characteristics of the multiple devices. The malfunction analysis/prediction unit, when a malfunction or a sign indicating a stage leading to the malfunction has occurred during an inspection, analyzes history information of the prober and tester related to the malfunction to determine or predict a location of the malfunction.Type: ApplicationFiled: January 30, 2018Publication date: January 9, 2020Inventor: Tetsuya KAGAMI
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Publication number: 20200011925Abstract: An inspection system includes a plurality of prober units each configured to bring probes of a probe card into contact with devices formed on a substrate on a stage, and a tester configured to apply electrical signals to the devices on the substrate through the probe card to inspect electrical characteristics of the devices. The plurality of prober units are arranged such that a plurality of units each of which has the prober units stacked in multiple stages are arranged in multiple rows in a horizontal direction, and at least one test unit constituting a main part of the tester is arranged to a side of a predetermined prober unit among the plurality of prober units.Type: ApplicationFiled: February 1, 2018Publication date: January 9, 2020Inventor: Tetsuya KAGAMI
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Publication number: 20170256324Abstract: A signal input/output circuit is provided with an input line, a common output line, a plurality of individual output lines, relay switches, and resistor elements. The common output line is connected to a comparator. The common output line synthesizes response signals transmitted from a plurality of devices under test (DUT), and transmits a synthesized response signal generated by synthesizing, into one signal, the response signals outputted from the respective DUTs. In response to a test signal transmitted from a pattern generator, the comparator compares the synthesized response signal with a threshold value.Type: ApplicationFiled: June 10, 2015Publication date: September 7, 2017Inventors: Tetsuya KAGAMI, Kanji SUZUKI
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Patent number: 7912696Abstract: A natural language processing apparatus includes an input section for inputting natural language, a representation converting section for converting representation of the natural language, a display section for displaying, for confirmation, sentence converted at the representation converting section, a machine translation section for carrying out machine translation of the confirmed sentence, and a control section for controlling these respective sections, thus to provide natural language processing in which confirmation operation of user is reduced.Type: GrantFiled: August 31, 1999Date of Patent: March 22, 2011Assignee: Sony CorporationInventors: Yasuharu Asano, Atsuo Hiroe, Masato Shimakawa, Tetsuya Kagami, Erika Kobayashi
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Patent number: 6529802Abstract: A robot provides a communicating means to move based on the transmission and reception of information to/from the outside, thereby making it possible to realize a robot with high usability. In addition, it recognizes the user's condition based on sensors provided around a user and outputs a response message according to the recognition. Thus, an information processing system which is very helpful can be realized.Type: GrantFiled: March 2, 2001Date of Patent: March 4, 2003Assignee: Sony CorporationInventors: Kozo Kawakita, Tadashi Ohtsuki, Yoshihiro Kuroki, Tetsuya Kagami, Tatsuzo Ishida
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Patent number: 6431544Abstract: A puzzle in the form of stacks which eliminates troublesome handling, and presents high versatility as amusement. An overall picture as a correct combination is divided into a plurality of segmental pictures which are separately displayed on different cards, each of which is placed in a plurality of cards belonging to one of stacks equal in number to the plurality of segmental pictures. A card displaying one of the segmental pictures is selected from a plurality of cards of each stack for exposure, and selected cards are placed in close proximity to assemble the segmental pictures to reconstruct the overall pictures on the cards.Type: GrantFiled: March 27, 2000Date of Patent: August 13, 2002Inventor: Tetsuya Kagami
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Patent number: 6161093Abstract: A book database stores at least phonetic signal information including phoneme information and rhythm information as document data, a central system transmits phonetic signal information stored on the book database to a terminal and the terminal receives the phonetic signal information is then carried out at the terminal and the document is then recited via synthesized sounds.Type: GrantFiled: October 1, 1998Date of Patent: December 12, 2000Assignee: Sony CorporationInventors: Masao Watari, Makoto Akabane, Tetsuya Kagami, Kazuo Ishii, Yusuke Iwahashi, Yasuhiko Kato, Hiroaki Ogawa, Masanori Omote, Kazuo Watanabe, Katsuki Minamino, Yasuharu Asano
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Apparatus and method for processing natural language and apparatus and method for speech recognition
Patent number: 5991721Abstract: An apparatus and a method for processing a natural language arranged so as to improve the speech recognition rate. In an example search section, the degree of similarity between each of a plurality of examples of the actual use of the language stored in an example data base and each of a plurality of probable recognition results output from a recognition section, and one of the examples corresponding to the highest degree of similarity is selected. A final speech recognition result is obtained by using the selected example. The example search section calculates the degree of similarity by weighting the degree of similarity on the basis of a context according to at least one of the examples previously selected.Type: GrantFiled: May 29, 1996Date of Patent: November 23, 1999Assignee: Sony CorporationInventors: Yasuharu Asano, Masao Watari, Makoto Akabane, Tetsuya Kagami, Kazuo Ishii, Miyuki Tanaka, Yasuhiko Kato, Hiroshi Kakuda, Hiroaki Ogawa -
Patent number: 5963892Abstract: A translation apparatus and a translation method arranged to facilitate the operation of inputting a speech and to obtain a correct translation. When a speech in Japanese is input to a microphone by a user, it is recognized in a speech recognition section and one or more words constituting the speech are output to a system control section. The system control section searches Japanese sentences stored in a first language sentence storage section to find one of them most similar to a combination of one or more words output from the speech recognition section. The Japanese sentence thereby found is output through an output section. If this Japanese sentence is correct, the user operates one of control keys. The system control section then searches English sentences stored in a second language sentence storage section to find one of them corresponding to a translation of the Japanese sentence output as a search result, and outputs the English sentence thereby found through the output section.Type: GrantFiled: June 26, 1996Date of Patent: October 5, 1999Assignee: Sony CorporationInventors: Miyuki Tanaka, Hiroaki Ogawa, Yasuhiko Kato, Tetsuya Kagami, Masao Watari, Makoto Akabane, Kazuo Ishii, Yasuharu Asano, Hiroshi Kakuda
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Patent number: 5903867Abstract: A book database stores at least phonetic signal information including phoneme information and rhythm information as document data, a central system transmits phonetic signal information stored on the book database to a terminal and the terminal receives the phonetic signal information is then carried out at the terminal and the document is then recited via synthesized sounds.Type: GrantFiled: November 23, 1994Date of Patent: May 11, 1999Assignee: Sony CorporationInventors: Masao Watari, Makoto Akabane, Tetsuya Kagami, Kazuo Ishii, Yusuke Iwahashi, Yasuhiko Kato, Hiroaki Ogawa, Masanori Omote, Kazuo Watanabe, Katsuki Minamino, Yasuharu Asano
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Patent number: 5848389Abstract: In a speech recognizing apparatus, a grammatical qualification of a proposed speech recognition result candidate is judged without using a grammatical rule. The speech recognizing apparatus for performing sentence/speech recognition is comprised of an analyzing unit for acoustically analyzing speech inputted therein to extract a feature parameter of the inputted speech; a recognizing unit for recognizing the inputted speech based upon the feature parameter outputted from said analyzing unit to thereby a plurality of proposed recognition result candidates; an example data base for storing therein a plurality of examples; and an example retrieving unit for calculating a resemblance degree between each of said plurality of proposed recognition result candidates and each of the plural examples stored in the example data base and for obtaining the speech recognition result based on said calculated resemblance degree.Type: GrantFiled: April 5, 1996Date of Patent: December 8, 1998Assignee: Sony CorporationInventors: Yasuharu Asano, Hiroaki Ogawa, Yasuhiko Kato, Tetsuya Kagami, Masao Watari, Makoto Akabane, Kazuo Ishii, Miyuki Tanaka, Hiroshi Kakuda