Patents by Inventor Tetsuya Katoh
Tetsuya Katoh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11667247Abstract: An ultrasonic sensor includes: an ultrasonic element provided to transmit or receive an ultrasonic wave propagating along a directional axis; and an element housing case that includes a case diaphragm having a thickness direction along the directional axis. A resonant space is defined between the case diaphragm and the ultrasonic element for the propagating wave, by housing the ultrasonic element while separating the ultrasonic element from the case diaphragm. A horn shape is defined in the element housing case in which a width of the resonant space in a direction orthogonal to the directional axis is reduced as the resonant space extends in an axial direction parallel to the directional axis.Type: GrantFiled: July 7, 2020Date of Patent: June 6, 2023Assignee: DENSO CORPORATIONInventors: Tatsuya Kamiya, Itaru Ishii, Tomoki Tanemura, Takashi Aoki, Tetsuya Katoh
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Patent number: 11445304Abstract: An ultrasonic sensor includes: an element storage case including a case-side diaphragm having a thickness direction along a directional axis; and an ultrasonic element accommodated in the element storage case and spaced apart from the case-side diaphragm. The ultrasonic element includes an element-side diaphragm having the thickness direction along the directional axis and provided by a thin part of a semiconductor substrate. The semiconductor substrate is arranged to provide a closed space between the case-side diaphragm and the element-side diaphragm. The semiconductor substrate is fixed and supported by the element-storage case.Type: GrantFiled: April 1, 2020Date of Patent: September 13, 2022Assignee: DENSO CORPORATIONInventors: Tatsuya Kamiya, Itaru Ishii, Tomoki Tanemura, Takashi Aoki, Tetsuya Katoh
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Publication number: 20210009046Abstract: An ultrasonic sensor includes: an ultrasonic element provided to transmit or receive an ultrasonic wave propagating along a directional axis; and an element housing case that includes a case diaphragm having a thickness direction along the directional axis. A resonant space is defined between the case diaphragm and the ultrasonic element for the propagating wave, by housing the ultrasonic element while separating the ultrasonic element from the case diaphragm. A horn shape is defined in the element housing case in which a width of the resonant space in a direction orthogonal to the directional axis is reduced as the resonant space extends in an axial direction parallel to the directional axis.Type: ApplicationFiled: July 7, 2020Publication date: January 14, 2021Inventors: Tatsuya KAMIYA, Itaru ISHII, Tomoki TANEMURA, Takashi AOKI, Tetsuya KATOH
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Publication number: 20200322730Abstract: An ultrasonic sensor includes: an element storage case including a case-side diaphragm having a thickness direction along a directional axis; and an ultrasonic element accommodated in the element storage case and spaced apart from the case-side diaphragm. The ultrasonic element includes an element-side diaphragm having the thickness direction along the directional axis and provided by a thin part of a semiconductor substrate. The semiconductor substrate is arranged to provide a closed space between the case-side diaphragm and the element-side diaphragm. The semiconductor substrate is fixed and supported by the element-storage case.Type: ApplicationFiled: April 1, 2020Publication date: October 8, 2020Inventors: Tatsuya KAMIYA, Itaru ISHII, Tomoki TANEMURA, Takashi AOKI, Tetsuya KATOH
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Patent number: 9658121Abstract: A load sensor is constituted by a rib and a vertical transistor including an organic semiconductor film, and a load measurement can be executed based on a change of a gap between a drain electrode and a source electrode which is a channel length of the vertical transistor. Therefore, a change of a current Ids is in a linear relationship to a load applied to the load sensor.Type: GrantFiled: July 30, 2014Date of Patent: May 23, 2017Assignee: DENSO CORPORATIONInventors: Takashi Inoue, Kensuke Hata, Tetsuya Katoh, Kenichi Sakai, Mayumi Uno, Junichi Takeya
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Publication number: 20160202132Abstract: A load sensor is constituted by a rib and a vertical transistor including an organic semiconductor film, and a load measurement can be executed based on a change of a gap between a drain electrode and a source electrode which is a channel length of the vertical transistor. Therefore, a change of a current Ids is in a linear relationship to a load applied to the load sensor.Type: ApplicationFiled: July 30, 2014Publication date: July 14, 2016Inventors: Takashi INOUE, Kensuke HATA, Tetsuya KATOH, Kenichi SAKAI, Mayumi UNO, Junichi TAKEYA
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Patent number: 8461572Abstract: There is provided a polymer or low-molecular-weight compound multilayer type organic EL device configured such that a light-emitting layer formed on a hole transport layer includes a mixture of a polymer material and a low-molecular weight material. With such a configuration, the low-molecular-weight material added to the polymer material serves as a binder filling the gap of the steric hindrance to form entanglement of the polymer material and the low-molecular-weight material. This results in that the interface between the hole transport layer and the light-emitting layer is an interface high in adhesion and also high in carrier injectability. Further, optimization of the formation conditions and materials can achieve still higher reliability and longer lifetime.Type: GrantFiled: May 14, 2009Date of Patent: June 11, 2013Assignees: DENSO CORPORATION, Kabushiki Kaisha Toyota Chuo KenkyushoInventors: Masayuki Katayama, Kazushige Kojima, Tetsuya Katoh, Kunio Akedo, Toshikazu Satoh, Koji Noda, Tomohiko Mori, Yoshihiro Kikuzawa, Koichi Sakaguchi
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Patent number: 8009128Abstract: A passive matrix type display device includes: a display unit having a display area; first electrodes on the area for switching between a conductive state and a non-conductive state; second electrodes on the area; a driving current source for supplying a driving current to the second electrodes; light-emitting elements at an intersection between the first and second electrodes; a first circuit for controlling a part of first electrodes to the conductive state and for scanning the first electrodes; a second circuit for deciding a part of second electrodes corresponding to a part of light-emitting elements emitting a light; light-emission adjustment elements coupled with the second electrodes for branching an adjustment current from the driving current; and a light-emission adjustment controller for controlling the light from each light-emitting element by controlling the adjustment current.Type: GrantFiled: July 19, 2007Date of Patent: August 30, 2011Assignee: DENSO CORPORATIONInventors: Takashi Hanaki, Hiroyuki Kishita, Tetsuya Katoh
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Publication number: 20110006288Abstract: There is provided a polymer or low-molecular-weight compound multilayer type organic EL device configured such that a light-emitting layer formed on a hole transport layer includes a mixture of a polymer material and a low-molecular weight material. With such a configuration, the low-molecular-weight material added to the polymer material serves as a binder filling the gap of the steric hindrance to form entanglement of the polymer material and the low-molecular-weight material. This results in that the interface between the hole transport layer and the light-emitting layer is an interface high in adhesion and also high in carrier injectability. Further, optimization of the formation conditions and materials can achieve still higher reliability and longer lifetime.Type: ApplicationFiled: May 14, 2009Publication date: January 13, 2011Inventors: Masayuki Katayama, Kazushige Kojima, Tetsuya Katoh, Kunio Akedo, Toshikazu Satoh, Koji Noda, Tomohiko Mori, Yoshihiro Kikuzawa, Koichi Sakaguchi
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Patent number: 7682880Abstract: Primitive cells, which are circuit patterns of the constituent elements of a semiconductor device, are arranged in the element formation area of a semiconductor device, and at least one fill cell with a diffusion layer and no wiring, is arranged in the vacant areas that are generated in the element formation area after the primitive cells have been arranged.Type: GrantFiled: March 14, 2007Date of Patent: March 23, 2010Assignee: NEC Electronics CorporationInventors: Hidekazu Kawashima, Tetsuya Katoh
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Patent number: 7576405Abstract: A semiconductor device is composed of: a power control region within which function cells are arranged; a basic power supply line overlapping said power control region, and positioned in a power supply interconnection layer; a virtual power supply line arranged in said power control region in a direction perpendicular to said basic power supply line, said function cells being connected to said virtual power supply line; a ground line arranged in said power control region in said direction perpendicular to said basic power supply line; a switch cell including a metal interconnection positioned in a metal interconnection layer different from said power supply interconnection layer, and a switch element electrically connected between said metal interconnection and said virtual power supply line; and a via contact connected between said basic power supply line and said metal interconnection. The switch cell is positioned within power control region.Type: GrantFiled: September 26, 2006Date of Patent: August 18, 2009Assignee: NEC Electronics CorporationInventor: Tetsuya Katoh
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Patent number: 7495269Abstract: A semiconductor device contains a semiconductor chip, and includes first and second circuits, a control signal line and a terminal. The first circuit is arranged in a center of the semiconductor chip and is configured to operate at a first voltage. The second circuit is arranged in an input/output circuit area around the first circuit on the semiconductor chip, and is configured to operate at the first voltage and a second voltage and to transfer a signal between an external unit outside the semiconductor chip and the first circuit. The control signal line is provided for the input/output circuit area on the semiconductor chip. The terminal is connected with the control signal line and supplied with a control signal. The second circuit stops a transfer of the signal between the external unit and the first circuit in response to the control signal which is transferred on the control signal line.Type: GrantFiled: August 16, 2005Date of Patent: February 24, 2009Assignee: NEC Electronics CorporationInventor: Tetsuya Katoh
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Publication number: 20080048952Abstract: A passive matrix type display device includes: a display unit having a display area; first electrodes on the area for switching between a conductive state and a non-conductive state; second electrodes on the area; a driving current source for supplying a driving current to the second electrodes; light-emitting elements at an intersection between the first and second electrodes; a first circuit for controlling a part of first electrodes to the conductive state and for scanning the first electrodes; a second circuit for deciding a part of second electrodes corresponding to a part of light-emitting elements emitting a light; light-emission adjustment elements coupled with the second electrodes for branching an adjustment current from the driving current; and a light-emission adjustment controller for controlling the light from each light-emitting element by controlling the adjustment current.Type: ApplicationFiled: July 19, 2007Publication date: February 28, 2008Applicant: DENSO CORPORATIONInventors: Takashi Hanaki, Hiroyuki Kishita, Tetsuya Katoh
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Publication number: 20070155061Abstract: Primitive cells, which are circuit patterns of the constituent elements of a semiconductor device, are arranged in the element formation area of a semiconductor device, and at least one fill cell with a diffusion layer and no wiring, is arranged in the vacant areas that are generated in the element formation area after the primitive cells have been arranged.Type: ApplicationFiled: March 14, 2007Publication date: July 5, 2007Inventors: Hidekazu Kawashima, Tetsuya Katoh
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Patent number: 7208350Abstract: Primitive cells, which are circuit patterns of the constituent elements of a semiconductor device, are arranged in the element formation area of a semiconductor device, and at least one fill cell with a diffusion layer and no wiring, is arranged in the vacant areas that are generated in the element formation area after the primitive cells have been arranged.Type: GrantFiled: January 13, 2004Date of Patent: April 24, 2007Assignee: NEC Electronics CorporationInventors: Hidekazu Kawashima, Tetsuya Katoh
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Publication number: 20070074134Abstract: A semiconductor device is composed of: a power control region within which function cells are arranged; a basic power supply line overlapping said power control region, and positioned in a power supply interconnection layer; a virtual power supply line arranged in said power control region in a direction perpendicular to said basic power supply line, said function cells being connected to said virtual power supply line; a ground line arranged in said power control region in said direction perpendicular to said basic power supply line; a switch cell including a metal interconnection positioned in a metal interconnection layer different from said power supply interconnection layer, and a switch element electrically connected between said metal interconnection and said virtual power supply line; and a via contact connected between said basic power supply line and said metal interconnection. The switch cell is positioned within power control region.Type: ApplicationFiled: September 26, 2006Publication date: March 29, 2007Applicant: NEC ELECTRONICS CORPORATIONInventor: Tetsuya Katoh
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Patent number: 7103866Abstract: To design a chip having a plurality of circuit areas driven by different power supplies, a boundary cell to be inserted on the boundary between the circuit areas is prepared. After creating a logic circuit netlist with a design tool, the boundary cell is inserted on the boundary. The boundary cell is connected on a signal transmission path between the circuit areas. A circuit for suppressing shoot-through current or leakage current is used as the boundary circuit. By preparing the boundary cell in a cell library, chip design is facilitated.Type: GrantFiled: April 23, 2004Date of Patent: September 5, 2006Assignee: NEC Electronics CorporationInventors: Yoshiki Kashiwagi, Tetsuya Katoh
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Publication number: 20060038277Abstract: A semiconductor device contains a semiconductor chip, and includes first and second circuits, a control signal line and a terminal. The first circuit is arranged in a center of the semiconductor chip and is configured to operate in a first voltage. The second circuit is arranged in an input/output circuit area around the first circuit on the semiconductor chip, and is configured to operate in the first voltage and a second voltage and to transfer a signal between an external unit outside the semiconductor chip and the first circuit. The control signal line is provided for the input/output circuit area on the semiconductor chip. The terminal is connected with the control signal line and supplied with a control signal. The second circuit stops a transfer of the signal between the external unit and the first circuit in response to the control signal which is transferred on the control signal line.Type: ApplicationFiled: August 16, 2005Publication date: February 23, 2006Applicant: NEC Electronics CorporationInventor: Tetsuya Katoh
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Publication number: 20040230769Abstract: Primitive cells, which are circuit patterns of the constituent elements of a semiconductor device, are arranged in the element formation area of a semiconductor device, and at least one fill cell with a diffusion layer and no wiring, is arranged in the vacant areas that are generated in the element formation area after the primitive cells have been arranged.Type: ApplicationFiled: January 13, 2004Publication date: November 18, 2004Inventors: Hidekazu Kawashima, Tetsuya Katoh
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Publication number: 20040225985Abstract: To design a chip having a plurality of circuit areas driven by different power supplies, a boundary cell to be inserted on the boundary between the circuit areas is prepared. After creating a logic circuit netlist with a design tool, the boundary cell is inserted on the boundary. The boundary cell is connected on a signal transmission path between the circuit areas. A circuit for suppressing short-through current or leakage current is used as the boundary circuit. By preparing the boundary cell in a cell library, chip design is facilitated.Type: ApplicationFiled: April 23, 2004Publication date: November 11, 2004Applicant: NEC Electronics CorporationInventors: Yoshiki Kashiwagi, Tetsuya Katoh