Patents by Inventor Tetsuya Kitame
Tetsuya Kitame has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6633508Abstract: Two memory cells in different memory arrays are simultaneously selected in accordance with the designation of a specific write operation mode to associate a logic 1 of a write signal with a state in which an electric charge exists in each capacitor. Further, a logic 0 of the write signal is associated with a state in which no electric charge exists in the capacitor to write the same write signal. Two dynamic memory cells in different memory arrays are simultaneously selected in accordance with the designation of a specific read operation mode to associate a state in which an electric charge exists in a capacitor of each dynamic memory cell with a logic 1 of a read signal and associate a state in which no electric charge exists in the capacitor with a logic 0 of the read signal in response to a write operation. Thus, the logics 1 of the two read signals are preferentially output.Type: GrantFiled: August 28, 2001Date of Patent: October 14, 2003Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp.Inventors: Masaya Muranaka, Shinichi Miyatake, Yukihide Suzuki, Kanehide Kenmizaki, Makoto Morino, Tetsuya Kitame
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Publication number: 20020031036Abstract: Two memory cells in different memory arrays are simultaneously selected in accordance with the designation of a specific write operation mode to associate a logic 1 of a write signal with a state in which an electric charge exists in each capacitor. Further, a logic 0 of the write signal is associated with a state in which no electric charge exists in the capacitor to write the same write signal. Two dynamic memory cells in different memory arrays are simultaneously selected in accordance with the designation of a specific read operation mode to associate a state in which an electric charge exists in a capacitor of each dynamic memory cell with a logic 1 of a read signal and associate a state in which no electric charge exists in the capacitor with a logic 0 of the read signal in response to a write operation. Thus, the logics 1 of the two read signals are preferentially output.Type: ApplicationFiled: August 28, 2001Publication date: March 14, 2002Inventors: Masaya Muranaka, Shinichi Miyatake, Yukihide Suzuki, Kanehide Kenmizaki, Makoto Morino, Tetsuya Kitame
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Patent number: 6282141Abstract: Two memory cells in different memory arrays are simultaneously selected in accordance with the designation of a specific write operation mode to associate a logic 1 of a write signal with a state in which an electric charge exists in each capacitor. Further, a logic 0 of the write signal is associated with a state in which no electric charge exists in the capacitor to write the same write signal. Two dynamic memory cells in different memory arrays are simultaneously selected in accordance with the designation of a specific read operation mode to associate a state in which an electric charge exists in a capacitor of each dynamic memory cell with a logic 1 of a read signal and associate a state in which no electric charge exists in the capacitor with a logic 0 of the read signal in response to a write operation. Thus, the logics 1 of the two read signals are preferentially output.Type: GrantFiled: May 15, 2000Date of Patent: August 28, 2001Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp.Inventors: Masaya Muranaka, Shinichi Miyatake, Yukihide Suzuki, Kanehide Kenmizaki, Makoto Morino, Tetsuya Kitame
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Patent number: 6064605Abstract: Two memory cells in different memory arrays are simultaneously selected in accordance with the designation of a specific write operation mode to associate a logic 1 of a write signal with a state in which an electric charge exists in each capacitor. Further, a logic 0 of the write signal is associated with a state in which no electric charge exists in the capacitor to write the same write signal. Two dynamic memory cells in different memory arrays are simultaneously selected in accordance with the designation of a specific read operation mode to associate a state in which an electric charge exists in a capacitor of each dynamic memory cell with a logic 1 of a read signal and associate a state in which no electric charge exists in the capacitor with a logic 0 of the read signal in response to a write operation. Thus, the logics 1 of the two read signals are preferentially output.Type: GrantFiled: September 14, 1999Date of Patent: May 16, 2000Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp.Inventors: Masaya Muranaka, Shinichi Miyatake, Yukihide Suzuki, Kanehide Kenmizaki, Makoto Morino, Tetsuya Kitame
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Patent number: 5969996Abstract: Two memory cells in different memory arrays are simultaneously selected in accordance with the designation of a specific write operation mode to associate a logic 1 of a write signal with a state in which an electric charge exists in each capacitor. Further, a logic 0 of the write signal is associated with a state in which no electric charge exists in the capacitor to write the same write signal. Two dynamic memory cells in different memory arrays are simultaneously selected in accordance with the designation of a specific read operation mode to associate a state in which an electric charge exists in a capacitor of each dynamic memory cell with a logic 1 of a read signal and associate a state in which no electric charge exists in the capacitor with a logic 0 of the read signal in response to a write operation. Thus, the logics 1 of the two read signals are preferentially output.Type: GrantFiled: August 31, 1998Date of Patent: October 19, 1999Assignee: Hiachi, Ltd.Inventors: Masaya Muranaka, Shinichi Miyatake, Yukihide Suzuki, Kanehide Kenmizaki, Makoto Morino, Tetsuya Kitame
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Patent number: 5818784Abstract: Two memory cells in different memory arrays are simultaneously selected in accordance with the designation of a specific write operation mode to associate a logic 1 of a write signal with a state in which an electric charge exists in each capacitor. Further, a logic 0 of the write signal is associated with a state in which no electric charge exists in the capacitor to write the same write signal. Two dynamic memory cells in different memory arrays are simultaneously selected in accordance with the designation of a specific read operation mode to associate a state in which an electric charge exists in a capacitor of each dynamic memory cell with a logic 1 of a read signal and associate a state in which no electric charge exists in the capacitor with a logic 0 of the read signal in response to a write operation. Thus, the logics 1 of the two read signals are preferentially output.Type: GrantFiled: April 26, 1996Date of Patent: October 6, 1998Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp.Inventors: Masaya Muranaka, Shinichi Miyatake, Yukihide Suzuki, Kanehide Kenmizaki, Makoto Morino, Tetsuya Kitame
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Patent number: 5598373Abstract: A defect remedy LSI mounted on a memory module, comprising: an input interface portion for capturing address and control signals, the input interface portion being the same as that of a dynamic RAM; an input/output interface portion corresponding to a data bus of a memory device comprised of a plurality of dynamic random access memories; a memory circuit to which a chip address and an X defective address of any of the plurality of random access memories are electrically written, the memory circuit being substantially made nonvolatile; a redundancy remedy RAM portion composed of a static RAM wherein a word line is selected by a compare match signal between an X address signal and the defective address of the memory circuit, the X address signal and the defective address being captured via the input interface portion, and a column is selected by a Y address signal captured via the input interface portion; a selecting portion for connecting a data input/output bus of the redundancy remedy RAM portion to an inputType: GrantFiled: June 7, 1995Date of Patent: January 28, 1997Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp.Inventors: Shoji Wada, Kanehide Kenmizaki, Masaya Muranaka, Masahiro Ogata, Hidetomo Aoyagi, Tetsuya Kitame, Masahiro Katayama, Shoji Kubono, Yukihide Suzuki, Makoto Morino, Sinichi Miyatake, Seiichi Shundo, Yoshihisa Koyama, Nobuhiko Ohno