Patents by Inventor Tetsuya Kurokawa
Tetsuya Kurokawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7800229Abstract: An improved SIV resistance and an improved EM resistance are achieved in the coupling structure containing copper films. A semiconductor device includes: a semiconductor substrate; a second insulating layer formed on or over the semiconductor substrate; a second barrier metal film, formed on the second insulating film, and being capable of preventing copper from diffusing into the second insulating film; and an electrically conducting film formed on the second barrier metal film so as to be in contact with the second barrier metal film, and containing copper and carbon, wherein a distribution of carbon concentration along a depositing direction in the second electrically conducting film includes a first peak and a second peak.Type: GrantFiled: February 12, 2007Date of Patent: September 21, 2010Assignee: NEC Electronics CorporationInventors: Akira Furuya, Koji Arita, Tetsuya Kurokawa, Kaori Noda
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Publication number: 20100078820Abstract: A metal barrier film which contains an additive element is formed on the side face and on the bottom of a trench formed in an insulating film; a seed film is formed over the metal barrier film; a plated layer (Cu film) is formed using the seed film as a seed so as to fill up the trench with a metal film; the metal barrier film and the metal film are annealed to thereby form therebetween an alloy layer which contains a metal composing the metal barrier film, the additive element, and a metal composing the metal film, and to thereby allow the additive element to diffuse into the metal film.Type: ApplicationFiled: September 30, 2009Publication date: April 1, 2010Applicant: NEC ELECTRONICS CORPORATIONInventors: TETSUYA KUROKAWA, MAKOTO TOHARA
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Publication number: 20080203572Abstract: The present invention provides a semiconductor device having interconnects, reduced in leakage current between the interconnects and improved in the TDDB characteristic, which comprises an insulating interlayer 108, and interconnects 160 filled in grooves formed in the insulating interlayer, comprising a copper layer 124 mainly composed of copper, having the thickness smaller than the depth of the grooves, and a low-expansion metal layer 140, which is a metal layer having a heat expansion coefficient smaller than that of the copper layer, formed on the copper layer.Type: ApplicationFiled: April 29, 2008Publication date: August 28, 2008Applicant: NEC ELECTRONICS CORPORATIONInventors: Tetsuya KUROKAWA, Koji Arita
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Patent number: 7388291Abstract: A semiconductor device having interconnects is reduced in leakage current between the interconnects and improved in the TDDB characteristic. It includes an insulating interlayer 108, and interconnects 160 filled in grooves formed in the insulating interlayer, including a copper layer 124 mainly composed of copper, having the thickness smaller than the depth of the grooves, and a low-expansion metal layer 140, which is a metal layer having a heat expansion coefficient smaller than that of the copper layer, formed on the copper layer.Type: GrantFiled: February 24, 2005Date of Patent: June 17, 2008Assignee: NEC Electronics CorporationInventors: Tetsuya Kurokawa, Koji Arita
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Publication number: 20080029402Abstract: An electrochemical processing apparatus is provided, in which a substrate and an anode placed in a chamber are partitioned into a cathode region including the substrate and an anode region including the anode by placing a multi-layered structure of a filtration film and a cation exchange film so that the filtration film is positioned on the substrate side. A plating solution containing additives is introduced into the cathode region, whereby a substrate is plated.Type: ApplicationFiled: July 31, 2007Publication date: February 7, 2008Applicant: NEC ELECTRONICS CORPORATIONInventors: Tetsuya Kurokawa, Koji Arita, Kaori Noda
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Publication number: 20070190341Abstract: An improved SIV resistance and an improved EM resistance are achieved in the coupling structure containing copper films. A semiconductor device includes: a semiconductor substrate; a second insulating layer formed on or over the semiconductor substrate; a second barrier metal film, formed on the second insulating film, and being capable of preventing copper from diffusing into the second insulating film; and an electrically conducting film formed on the second barrier metal film so as to be in contact with the second barrier metal film, and containing copper and carbon, wherein a distribution of carbon concentration along a depositing direction in the second electrically conducting film includes a first peak and a second peak.Type: ApplicationFiled: February 12, 2007Publication date: August 16, 2007Applicant: NEC ELECTRONICS CORPORATIONInventors: Akira Furuya, Koji Arita, Tetsuya Kurokawa, Kaori Noda
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Patent number: 7230337Abstract: The present invention reduces the effective dielectric constant of the interlayer insulating film while inhibiting the decrease of the reliability of the semiconductor device, which otherwise is caused by a moisture absorption. A copper interconnect comprising a Cu film 209 is formed in multilayer films comprising a L-Ox™ film 203 and a SiO2 film 204. Since the L-Ox™ film 203 comprises ladder-shaped siloxane hydride structure, the film thickness and the film characteristics are stable, and thus changes in the film quality is scarcely occurred during the manufacturing process.Type: GrantFiled: January 21, 2004Date of Patent: June 12, 2007Assignee: NEC Electronics CorporationInventors: Tatsuya Usami, Takashi Ishigami, Tetsuya Kurokawa, Noriaki Oda
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Publication number: 20060276029Abstract: The present invention reduces the effective dielectric constant of the interlayer insulating film while inhibiting the decrease of the reliability of the semiconductor device, which otherwise is caused by a moisture absorption. A copper interconnect comprising a Cu film 209 is formed in multilayer films comprising a L-Ox™ film 203 and a SiO2 film 204. Since the L-Ox™ film 203 comprises ladder-shaped siloxane hydride structure, the film thickness and the film characteristics are stable, and thus changes in the film quality is scarcely occurred during the manufacturing process.Type: ApplicationFiled: August 15, 2006Publication date: December 7, 2006Inventors: Tatsuya Usami, Takashi Ishigami, Tetsuya Kurokawa, Noriaki Oda
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Patent number: 7138700Abstract: A semiconductor device has a first guard ring surrounding a circuit region, a second ring disposed between the circuit region and the first guard ring, and first connections connecting the first guard ring and the second guard ring to each other. An area sandwiched between the first guard ring and the second guard ring is divided by the first connections into a plurality of subareas. Even if the first guard ring is partly defective, water enters from outside into only the subarea which is contiguous to the defective part of the first guard ring.Type: GrantFiled: March 24, 2004Date of Patent: November 21, 2006Assignee: NEC Electronics CorporationInventors: Ryuji Tomita, Tetsuya Kurokawa, Takashi Ishigami, Manabu Iguchi, Kazuyoshi Ueno, Makoto Sekine
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Publication number: 20050189654Abstract: A semiconductor device having interconnects is reduced in leakage current between the interconnects and improved in the TDDB characteristic. It includes an insulating interlayer 108, and interconnects 160 filled in grooves formed in the insulating interlayer, including a copper layer 124 mainly composed of copper, having the thickness smaller than the depth of the grooves, and a low-expansion metal layer 140, which is a metal layer having a heat expansion coefficient smaller than that of the copper layer, formed on the copper layer.Type: ApplicationFiled: February 24, 2005Publication date: September 1, 2005Applicant: NEC ELECTRONICS CORPORATIONInventors: Tetsuya Kurokawa, Koji Arita
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Publication number: 20040195582Abstract: A semiconductor device has a first guard ring surrounding a circuit region, a second ring disposed between the circuit region and the first guard ring, and first connections connecting the first guard ring and the second guard ring to each other. An area sandwiched between the first guard ring and the second guard ring is divided by the first connections into a plurality of subareas. Even if the first guard ring is partly defective, water enters from outside into only the subarea which is contiguous to the defective part of the first guard ring.Type: ApplicationFiled: March 24, 2004Publication date: October 7, 2004Applicant: NEC ELECTRONICS CORPORATIONInventors: Ryuji Tomita, Tetsuya Kurokawa, Takashi Ishigami, Manabu Iguchi, Kazuyoshi Ueno, Makoto Sekine
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Publication number: 20040173910Abstract: The present invention reduces the effective dielectric constant of the interlayer insulating film while inhibiting the decrease of the reliability of the semiconductor device, which otherwise is caused by a moisture absorption. A copper interconnect comprising a Cu film 209 is formed in multilayer films comprising a L-Ox™ film 203 and a SiO2 film 204. Since the L-Ox™ film 203 comprises ladder-shaped siloxane hydride structure, the film thickness and the film characteristics are stable, and thus changes in the film quality is scarcely occurred during the manufacturing process.Type: ApplicationFiled: January 21, 2004Publication date: September 9, 2004Applicant: NEC Electronics CorporationInventors: Tatsuya Usami, Takashi Ishigami, Tetsuya Kurokawa, Noriaki Oda
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Patent number: 6207106Abstract: Hydrogen sulfide is dehydrogenated to generate a HS group and an S group. The HS group is oxidized to generate sulfuric acid, which is bonded to a metal. The S group is polymerized with a CH3S group to generate methyl trisulfide or methyl tetrasulfide, which is adsorbed to an adsorbent. Methyl mercaptan is dehydrogenated, for example, to generate a CH3S group. A portion of the CH3S group is oxidized to generate methanesulfonic acid, which is bonded to a metal. Another portion of the CH3S group is polymerized with the CH3S group itself to generate methyl disulfide, at least a portion of which is adsorbed to an adsorbent. Still another portion of the CH3S group is polymerized with the S group to generate methyl trisulfide or methyl tetrasulfide, which is physically adsorbed to an adsorbent. In this manner, malodor components including hydrogen sulfide and methyl mercaptan can efficiently be removed without producing or release of harmful secondary products.Type: GrantFiled: September 30, 1999Date of Patent: March 27, 2001Assignee: Toto, Ltd.Inventors: Tetsuya Kurokawa, Chihiro Kobayashi, Tomonori Tokumoto, Masahiro Yamamoto, Takashi Tsuchida
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Patent number: 6010666Abstract: Hydrogen sulfide is dehydrogenated to generate a HS group and an S group. The HS group is oxidized to generate sulfuric acid, which is bonded to a metal. The S group is polymerized with a CH.sub.3 S group to generate methyl trisulfide or methyl tetrasulfide, which is adsorbed to an adsorbent. Methyl mercaptan is dehydrogenated, for example, to generate a CH.sub.3 S group. A portion of the CH.sub.3 S group is oxidized to generate methanesulfonic acid, which is bonded to a metal. Another portion of the CH.sub.3 S group is polymerized with the CH.sub.3 S group itself to generate methyl disulfide, at least a portion of which is adsorbed to an adsorbent. Still another portion of the CH.sub.3 S group is polymerized with the S group to generate methyl trisulfide or methyl tetrasulfide, which is physically adsorbed to an adsorbent. In this manner, malodor components including hydrogen sulfide and methyl mercaptan can efficiently be removed without producing or release of harmful secondary products.Type: GrantFiled: November 15, 1996Date of Patent: January 4, 2000Assignee: Toto, Ltd.Inventors: Tetsuya Kurokawa, Chihiro Kobayashi, Tomonori Tokumoto, Masahiro Yamamoto, Takashi Tsuchida
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Patent number: 5844306Abstract: A lead frame having a die pad of such a shape that prevents scattering of solder to lead when a chip is mounted on the lead frame, and a semiconductor device using such a lead frame are provided. The lead frame includes a die pad having a region surrounded by a first side, a second side opposing to the first side, a third side different from the first and second sides, and a fourth side opposing to the third side, and a lead formed of a conductor and electrically connected to a semiconductor element. The die pad includes a notch extending along the first and the second sides and positioned opposing to a main surface of the semiconductor element, and a through hole extending along the third and fourth sides and positioned opposing to the main surface of the semiconductor element. The semiconductor device employs the die pad.Type: GrantFiled: January 24, 1996Date of Patent: December 1, 1998Assignees: Mitsubishi Denki Kabushiki Kaisha, Shikoku Instrumentation Co., Ltd.Inventors: Kazumoto Fujita, Takashi Iwata, Tetsuya Kurokawa