Patents by Inventor Tetsuya Ohnishi
Tetsuya Ohnishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9023948Abstract: It is an object of the invention to provide a chloroprene rubber-based polymer latex that has a good balance between initial adhesion and storage stability and is suitable for one-component aqueous adhesive applications. The invention relates to a chloroprene rubber-based polymer latex composition containing a mixture of a chloroprene rubber-based polymer latex and a latex of an acrylic or styrene-acrylic resin-based polymer obtained by copolymerization of a specific carboxyl group-containing unsaturated monomer, in which the specific carboxyl group is neutralized with an alkali.Type: GrantFiled: March 15, 2013Date of Patent: May 5, 2015Assignee: Showa Denko K.K.Inventor: Tetsuya Ohnishi
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Patent number: 8980722Abstract: A variable resistive element comprising a configuration that an area of an electrically contributing region of a variable resistor body is finer than that constrained by an upper electrode or a lower electrode and its manufacturing method are provided. A bump electrode material is formed on a lower electrode arranged on a base substrate. The bump electrode material is contacted to a variable resistor body at a surface different from a contact surface to the lower electrode. The variable resistor body is contacted to an upper electrode at a surface different from a contact surface to the bump electrode material. Thus, a cross point region between the bump electrode material (the variable resistor body) and the upper electrode becomes an electrically contributing region of the variable resistor body, and then an area thereof can be reduced compared with that of the region regarding the conventional variable resistive element.Type: GrantFiled: July 26, 2013Date of Patent: March 17, 2015Assignee: Xenogenic Development Limited Liability CompanyInventors: Yasunari Hosoi, Kazuya Ishihara, Takahiro Shibuya, Tetsuya Ohnishi, Takashi Nakano
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Publication number: 20150057399Abstract: It is an object of the invention to provide a chloroprene rubber-based polymer latex that has a good balance between initial adhesion and storage stability and is suitable for one-component aqueous adhesive applications. The invention relates to a chloroprene rubber-based polymer latex composition containing a mixture of a chloroprene rubber-based polymer latex and a latex of an acrylic or styrene-acrylic resin-based polymer obtained by copolymerization of a specific carboxyl group-containing unsaturated monomer, in which the specific carboxyl group is neutralized with an alkali.Type: ApplicationFiled: March 15, 2013Publication date: February 26, 2015Applicant: SHOWA DENKO K.K.Inventor: Tetsuya Ohnishi
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Publication number: 20140027703Abstract: A variable resistive element comprising a configuration that an area of an electrically contributing region of a variable resistor body is finer than that constrained by an upper electrode or a lower electrode and its manufacturing method are provided. A bump electrode material is formed on a lower electrode arranged on a base substrate. The bump electrode material is contacted to a variable resistor body at a surface different from a contact surface to the lower electrode. The variable resistor body is contacted to an upper electrode at a surface different from a contact surface to the bump electrode material. Thus, a cross point region between the bump electrode material (the variable resistor body) and the upper electrode becomes an electrically contributing region of the variable resistor body, and then an area thereof can be reduced compared with that of the region regarding the conventional variable resistive element.Type: ApplicationFiled: July 26, 2013Publication date: January 30, 2014Applicant: Xenogenic Development Limited Liability CompanyInventors: Yasunari Hosoi, Kazuya Ishihara, Takahiro Shibuya, Tetsuya Ohnishi, Takashi Nakano
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Patent number: 8497492Abstract: A variable resistive element comprising a configuration that an area of an electrically contributing region of a variable resistor body is finer than that constrained by an upper electrode or a lower electrode and its manufacturing method are provided. A bump electrode material is formed on a lower electrode arranged on a base substrate. The bump electrode material is contacted to a variable resistor body at a surface different from a contact surface to the lower electrode. The variable resistor body is contacted to an upper electrode at a surface different from a contact surface to the bump electrode material. Thus, a cross point region between the bump electrode material (the variable resistor body) and the upper electrode becomes an electrically contributing region of the variable resistor body, and then an area thereof can be reduced compared with that of the region regarding the conventional variable resistive element.Type: GrantFiled: February 23, 2007Date of Patent: July 30, 2013Assignee: Xenogenic Development Limited Liability CompanyInventors: Yasunari Hosoi, Kazuya Ishihara, Takahiro Shibuya, Tetsuya Ohnishi, Takashi Nakano
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Patent number: 8115586Abstract: Provided are a variable resistive element having a configuration that the area of an electrically contributing region in a variable resistor body is smaller than the area defined by an upper electrode or a lower electrode, and a method for manufacturing the variable resistive element. The cross section of a current path, in which an electric current flows through between the two electrodes via the variable resistor body at the time of applying the voltage pulse to between the two electrodes, is formed with a line width of narrower than that of any of the two electrodes and of smaller than a minimum work dimension regarding manufacturing processes, so that its area can be made smaller than that of the electrically contributing region in the variable resistive element of the prior art.Type: GrantFiled: February 16, 2007Date of Patent: February 14, 2012Assignee: Sharp Kabushiki KaishaInventors: Yasunari Hosoi, Kazuya Ishihara, Takahiro Shibuya, Tetsuya Ohnishi, Takashi Nakano
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Patent number: 8030695Abstract: A semiconductor memory device having a cross point structure includes a plurality of upper electrodes arranged to extend in one direction, and a plurality of lower electrodes arranged to extend in another direction at a right angle to the one direction of the upper electrodes. Memory materials are provided between the upper electrodes and the lower electrodes for storage of data. The memory materials are made of a perovskite material and arranged at the lower electrodes side of the corresponding upper electrode extending along the corresponding upper electrode.Type: GrantFiled: December 22, 2010Date of Patent: October 4, 2011Assignee: Sharp Kabushiki KaishaInventors: Tetsuya Ohnishi, Naoyuki Shinmura, Shinobu Yamazaki, Takahiro Shibuya, Takashi Nakano, Masayuki Tajiri, Shigeo Ohnishi
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Publication number: 20110089395Abstract: A semiconductor memory device having a cross point structure includes a plurality of upper electrodes arranged to extend in one direction, and a plurality of lower electrodes arranged to extend in another direction at a right angle to the one direction of the upper electrodes. Memory materials are provided between the upper electrodes and the lower electrodes for storage of data. The memory materials are made of a perovskite material and arranged at the lower electrodes side of the corresponding upper electrode extending along the corresponding upper electrode.Type: ApplicationFiled: December 22, 2010Publication date: April 21, 2011Applicant: Sharp Kabushiki KaishaInventors: Tetsuya OHNISHI, Naoyuki Shinmura, Shinobu Yamazaki, Takahiro Shibuya, Takashi Nakano, Masayuki Tajiri, Shigeo Ohnishi
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Patent number: 7879626Abstract: A semiconductor memory device having a cross point structure includes a plurality of upper electrodes arranged to extend in one direction, and a plurality of lower electrodes arranged to extend in another direction at a right angle to the one direction of the upper electrodes. Memory materials are provided between the upper electrodes and the lower electrodes for storage of data. The memory materials are made of a perovskite material and arranged at the lower electrodes side of the corresponding upper electrode extending along the corresponding upper electrode.Type: GrantFiled: November 16, 2005Date of Patent: February 1, 2011Assignee: Sharp Kabushiki KaishaInventors: Tetsuya Ohnishi, Naoyuki Shinmura, Shinobu Yamazaki, Takahiro Shibuya, Takashi Nakano, Masayuki Tajiri, Shigeo Ohnishi
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Publication number: 20100128512Abstract: A semiconductor memory device having a cross-point structure comprising a plurality of first electrode wirings extending in the same direction, a plurality of second electrode wirings intersecting with the first electrode wirings, and memory materials for storing data at the intersection points of the first and second electrode wirings has a problem that an effective voltage applied to the memory material fluctuates in a memory cell array due to the voltage drop caused by the wiring resistance of each electrode wiring. The sum of the wiring resistance of the first electrode wiring to a certain intersection point and the wiring resistance of the second electrode wiring to the certain intersection point is substantially constant at any intersection point, and the load resistors for adjusting the fluctuation of the electrode wiring resistances in a memory cell array are connected at least either one of the first and second electrode wirings.Type: ApplicationFiled: September 27, 2006Publication date: May 27, 2010Inventors: Tetsuya Ohnishi, Syogo Hayashi
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Patent number: 7615459Abstract: A manufacturing method for a variable resistive element according to which a stable switching operation can be achieved with excellent reproducibility is provided. A conductive thin film is deposited on a semiconductor substrate and patterned to a predetermined form, and after that, a first interlayer insulating film is deposited. An opening is then created in a predetermined location on the first interlayer insulating film in such a manner that the upper surface of the conductive thin film is exposed and the thickness of the conductive thin film formed at the bottom of this opening is reduced through processing, and after that, an oxidation process is carried out on the periphery of the exposed conductive thin film. As a result, a variable resistor film is formed in the peripheral region of the opening, and this variable resistor film divides the conductive thin film into a first electrode and a second electrode.Type: GrantFiled: August 12, 2008Date of Patent: November 10, 2009Assignee: Sharp Kabushiki KaishaInventors: Yushi Inoue, Tetsuya Ohnishi, Kazuya Ishihara, Takahiro Shibiuya, Yasunari Hosoi, Shinobu Yamazaki, Takashi Nakano
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Patent number: 7602026Abstract: A memory cell in a semiconductor memory device comprises a variable resistor element configured so that a variable resistor body is sandwiched between a first electrode and a second electrode, and a transistor element capable of controlling a flow of current in the variable resistor element, wherein the transistor element and the variable resistor element are placed one over the other along a direction in which the first electrode, the variable resistor body, and the second electrode of the variable resistor element are layered, and one of the first electrode and the second electrode of the variable resistor element is connected to one electrode of the transistor element.Type: GrantFiled: June 26, 2006Date of Patent: October 13, 2009Assignee: Sharp Kabushiki KaishaInventors: Shinji Horii, Takashi Yokoyama, Tetsuya Ohnishi
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Publication number: 20090200640Abstract: A variable resistive element comprising a configuration that an area of an electrically contributing region of a variable resistor body is finer than that constrained by an upper electrode or a lower electrode and its manufacturing method are provided. A bump electrode material is formed on a lower electrode arranged on a base substrate. The bump electrode material is contacted to a variable resistor body at a surface different from a contact surface to the lower electrode. The variable resistor body is contacted to an upper electrode at a surface different from a contact surface to the bump electrode material. Thus, a cross point region between the bump electrode material (the variable resistor body) and the upper electrode becomes an electrically contributing region of the variable resistor body, and then an area thereof can be reduced compared with that of the region regarding the conventional variable resistive element.Type: ApplicationFiled: February 23, 2007Publication date: August 13, 2009Inventors: Yasunari Hosoi, Kazuya Ishihara, Takahiro Shibuya, Tetsuya Ohnishi, Takashi Nakano
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Publication number: 20090096568Abstract: Provided are a variable resistive element having a configuration that the area of an electrically contributing region in a variable resistor body is smaller than the area defined by an upper electrode or a lower electrode, and a method for manufacturing the variable resistive element. The cross section of a current path, in which an electric current flows through between the two electrodes via the variable resistor body at the time of applying the voltage pulse to between the two electrodes, is formed with a line width of narrower than that of any of the two electrodes and of smaller than a minimum work dimension regarding manufacturing processes, so that its area can be made smaller than that of the electrically contributing region in the variable resistive element of the prior art.Type: ApplicationFiled: February 16, 2007Publication date: April 16, 2009Inventors: Yasunari Hosoi, Kazuya Ishihara, Takahiro Shibuya, Tetsuya Ohnishi, Takashi Nakano
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Patent number: 7167266Abstract: An image memory apparatus includes a unit for storing input image information, a unit for designating a storing capacity of the storing unit for the input image information, and a control unit for performing storing control of the storing unit for the input image information in accordance with an instruction from the designating unit.Type: GrantFiled: January 12, 2004Date of Patent: January 23, 2007Assignee: Canon Kabushiki KaishaInventors: Masanori Sakai, Toshihiro Kadowaki, Naoto Arakawa, Tetsuya Ohnishi
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Publication number: 20060289942Abstract: A memory cell in a semiconductor memory device comprises a variable resistor element configured so that a variable resistor body is sandwiched between a first electrode and a second electrode, and a transistor element capable of controlling a flow of current in the variable resistor element, wherein the transistor element and the variable resistor element are placed one over the other along a direction in which the first electrode, the variable resistor body, and the second electrode of the variable resistor element are layered, and one of the first electrode and the second electrode of the variable resistor element is connected to one electrode of the transistor element.Type: ApplicationFiled: June 26, 2006Publication date: December 28, 2006Applicant: SHARP KABUSHIKI KAISHAInventors: Shinji Horii, Takashi Yokoyama, Tetsuya Ohnishi
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Publication number: 20060154417Abstract: The present invention is directed towards a method of manufacturing a semiconductor memory device arranged of a cross point memory array having memory elements provided between upper and lower electrodes for storage of data. The present invention comprises a lower electrode lines forming step of planarizing each of the lower electrode lines and insulating layers provided on both sides of the lower electrode line so as to be substantially uniform in the height thus for patterning the lower electrode lines, a memory element layer depositing step of depositing on the lower electrode lines a memory element layer for the memory elements, and an annealing step of annealing with heat treatment either between the lower electrode lines forming step and the memory element layer depositing step or after the memory element layer depositing step so that any damages caused by the polishing of the surface of the lower electrode lines can be eliminated.Type: ApplicationFiled: January 11, 2006Publication date: July 13, 2006Applicant: SHARP KABUSHIKI KAISHAInventors: Naoyuki Shinmura, Shigeo Ohnishi, Tetsuya Ohnishi, Shinobu Yamazaki, Takahiro Shibuya, Takashi Nakano, Masayuki Tajiri
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Publication number: 20060102943Abstract: A semiconductor memory device having a cross point structure includes a plurality of upper electrodes arranged to extend in one direction, and a plurality of lower electrodes arranged to extend in another direction at a right angle to the one direction of the upper electrodes. Memory materials are provided between the upper electrodes and the lower electrodes for storage of data. The memory materials are made of a perovskite material and arranged at the lower electrodes side of the corresponding upper electrode extending along the corresponding upper electrode.Type: ApplicationFiled: November 16, 2005Publication date: May 18, 2006Applicant: SHARP KABUSHIKI KAISHAInventors: Tetsuya Ohnishi, Naoyuki Shinmura, Shinobu Yamazaki, Takahiro Shibuya, Takashi Nakano, Masayuki Tajiri, Shigeo Ohnishi
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Publication number: 20040141204Abstract: An image memory apparatus includes a unit for storing input image information, a unit for designating a storing capacity of the storing unit for the input image information, and a control unit for performing storing control of the storing unit for the input image information in accordance with an instruction from the designating unit.Type: ApplicationFiled: January 12, 2004Publication date: July 22, 2004Applicant: Canon Kabushiki KaishaInventors: Masanori Sakai, Toshihiro Kadowaki, Naoto Arakawa, Tetsuya Ohnishi
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Patent number: 6750100Abstract: A method of forming a memory device includes preparing a substrate having predefined characteristics; forming a first layer set on the substrate, including: building a first forming layer, having first form segments, on the substrate; building placeholder sidewalls on the first form segments wherein the sidewalls have a thickness of between about one nm and 100 nm; building a second forming layer, having second form segments, on the substrate between the placeholder sidewalls; removing the placeholder sidewalls forming vacated areas; and building active devices in the vacated areas.Type: GrantFiled: August 27, 2001Date of Patent: June 15, 2004Assignee: Sharp Laboratories of America, Inc.Inventors: Sheng Teng Hsu, Tomoya Baba, Tetsuya Ohnishi