Patents by Inventor Tetsuya Ootsuki
Tetsuya Ootsuki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7173227Abstract: A laser beam processing apparatus includes a laser oscillator for producing a laser beam for processing a processing object, a focus head for focusing the laser beam output from the laser oscillator onto the processing object, a photo detector for detecting light emanating from the processing object in response to irradiation with the laser beam and a reference light generated from a reference light generating unit via a nozzle attached to the focus head, a correlation adjusting unit for adjusting correlation between the light detected during the processing and processing state of the processing object from the reference light detected by the photo detector, and a control unit for controlling the laser oscillator by monitoring the processing situation of the processing object from the light detected during the processing and that is adjusted by the correlation adjusting unit.Type: GrantFiled: July 29, 2004Date of Patent: February 6, 2007Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Takaaki Iwata, Tetsuya Ootsuki
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Patent number: 6982923Abstract: In a semiconductor memory device, a plurality of memory cell arrays, and each of them includes a plurality of memory cells in a matrix. A mode control unit outputs a delay control signal, and an instruction execution unit accesses to the plurality of memory cells based on an address and an address buffer control signal supplied externally. A command control unit outputs the address buffer control signal to the instruction execution unit based on a command supplied externally and the delay control signal. The command control unit outputs the address buffer signal in synchronization with a clock signal when the delay control signal is in an inactive state and the command is a write command or a read command in an ordinary operation mode. When the delay control signal is in an active state and the command is the write command in a write instruction delay operation mode, also when the delay control signal is in the active state and the command is the read command in a read instruction delay operation mode.Type: GrantFiled: November 14, 2003Date of Patent: January 3, 2006Assignee: Elpida Memory, Inc.Inventor: Tetsuya Ootsuki
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Publication number: 20050199780Abstract: A laser beam processing apparatus includes a laser oscillator for producing a laser beam for processing a processing object, a focus head for focusing the laser beam output from the laser oscillator onto the processing object, a photo detector for detecting light emanating from the processing object in response to irradiation with the laser beam and a reference light generated from a reference light generating unit via a nozzle attached to the focus head, a correlation adjusting unit for adjusting correlation between the light detected during the processing and processing state of the processing object from the reference light detected by the photo detector, and a control unit for controlling the laser oscillator by monitoring the processing situation of the processing object from the light detected during the processing and that is adjusted by the correlation adjusting unit.Type: ApplicationFiled: July 29, 2004Publication date: September 15, 2005Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Takaaki Iwata, Tetsuya Ootsuki
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Publication number: 20040100856Abstract: In a semiconductor memory device, a plurality of memory cell arrays, and each of them includes a plurality of memory cells in a matrix. A mode control unit outputs a delay control signal, and an instruction execution unit accesses to the plurality of memory cells based on an address and an address buffer control signal supplied externally. A command control unit outputs the address buffer control signal to the instruction execution unit based on a command supplied externally and the delay control signal. The command control unit outputs the address buffer signal in synchronization with a clock signal when the delay control signal is in an inactive state and the command is a write command or a read command in an ordinary operation mode. When the delay control signal is in an active state and the command is the write command in a write instruction delay operation mode, also when the delay control signal is in the active state and the command is the read command in a read instruction delay operation mode.Type: ApplicationFiled: November 14, 2003Publication date: May 27, 2004Applicant: Elpida Memory, Inc.Inventor: Tetsuya Ootsuki
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Publication number: 20010005147Abstract: A semiconductor circuit is composed of an N-channel transistor, a driving circuit, and a charge pump. The N-channel transistor includes a gate and a drain. The drain is provided with a power supply potential. The driving circuit sets a gate potential at the gate to a first potential in response to an input signal. The charge pump raises the gate potential to a second potential higher than the first potential in response to the input signal.Type: ApplicationFiled: December 27, 2000Publication date: June 28, 2001Applicant: NEC CORPInventor: Tetsuya Ootsuki
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Patent number: 6130845Abstract: There is provided a dynamic type semiconductor memory device including (a) a first hierarchized complementary bit line, (b) a second hierarchized complementary bit line, (c) a first sense-amplifier electrically connected to the first bit line, (d) at least one second sense-amplifier electrically connected to both the first bit line and the second bit line, (e) a capacitor located between the first and second bit lines for each of second sense-amplifiers, and (f) a transfer gate arranged in series with the capacity between the first and second bit lines. The above-mentioned dynamic type semiconductor memory device makes it possible to store two-bit data in a single memory cell by employing a memory cell comprised of one transistor and one capacitor, without the use of a conventional memory cell having two transistors and one capacitor. Hence, the dynamic type semiconductor memory device ensures a significant reduction in a chip area.Type: GrantFiled: September 29, 1998Date of Patent: October 10, 2000Assignee: NEC CorporationInventors: Tetsuya Ootsuki, Isao Naritake
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Patent number: 5693984Abstract: A highly reliable semiconductor device and a method of manufacturing the same. The semiconductor device is constituted by a semiconductor element which is disposed within a space portion defined by leads of a lead frame or fixed to a die pad of a lead frame and which has bonding pads connected to the leads through wires respectively, and a heat radiation block/plate which is made of a good thermally conductive material and which has an outer periphery having a size sufficiently to overlap the leads so that the heat radiation block/plate is disposed on the leads partly through a tape-like insulator, the semiconductor element being disposed on a center portion of the heat radiation block/plate directly or through the die pad. The semiconductor device is sealed with resin or the like with part of the leads and an end surface of the heat radiation block/plate left exposed or with part of the leads left exposed.Type: GrantFiled: May 27, 1993Date of Patent: December 2, 1997Assignee: Seiko Epson CorporationInventor: Tetsuya Ootsuki
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Patent number: 5686361Abstract: A highly reliable semiconductor device and a method of manufacturing the same. The semiconductor device is constituted by a semiconductor element which is disposed within a space portion defined by leads of a lead frame or fixed to a die pad of a lead frame and which has bonding pads connected to the leads through wires respectively, and a heat radiation block/plate which is made of a good thermally conductive material and which has an outer periphery having a size sufficiently to overlap the leads so that the heat radiation block/plate is disposed on the leads partly through a tape-like insulator, the semiconductor element being disposed on a center portion of the heat radiation block/plate directly or through the die pad. The semiconductor device is sealed with resin or the like with part of the leads and an end surface of the heat radiation block/plate left exposed or with part of the leads left exposed.Type: GrantFiled: March 12, 1996Date of Patent: November 11, 1997Assignee: Seiko Epson CorporationInventor: Tetsuya Ootsuki
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Patent number: 5652461Abstract: A semiconductor device with a convex heat sink comprises: a semiconductor element disposed within a space formed by leads of a lead frame, the semiconductor element having bonding pads connected to the leads through wires respectively; a convex heat sink made from a high heat-conductive material and formed so as to have an outer periphery of a size sufficiently large to overlap the leads, the semiconductor element being disposed at a center portion of the heat sink; an insulator disposed on the leads and for bonding and fixing the semiconductor element to the heat sink; and a package of resin for sealing except part of the leads and the top surface of a projecting portion of the heat sink; wherein the insulator has a shape like a tape so as to cover part of the leads and extend along a bottom surface near a circumferential edge of the heat sink, and the side surface of the projecting portion of the heat sink is scraped out into a curved surface.Type: GrantFiled: July 5, 1994Date of Patent: July 29, 1997Assignee: Seiko Epson CorporationInventors: Tetsuya Ootsuki, Norikata Hama
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Patent number: 5230144Abstract: A lead frame having inner leads which secures predetermined mechanical strength and which has no possibility of generation of twisting or the like through working, and a method of producing such a lead frame.Type: GrantFiled: March 16, 1992Date of Patent: July 27, 1993Assignee: Seiko Epson CorporationInventor: Tetsuya Ootsuki