Patents by Inventor Tetsuya Shimomura
Tetsuya Shimomura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230023059Abstract: A lower structure for a hybrid automobile in which a high-voltage battery is disposed in a lower surface of a floor panel includes an engine exhaust system component which is disposed in front of the high-voltage battery in the lower surface of the floor panel and on one vehicle-width-direction side of a center in a vehicle width direction and high-voltage devices which are disposed in front of the high-voltage battery and on another vehicle-width-direction side of the center in the vehicle width direction. In-vehicle equipment is disposed between the high-voltage battery and the high-voltage devices, and the in-vehicle equipment is in an inclined state where an upper surface of the in-vehicle equipment is inclined in a front-rear direction such that the in-vehicle equipment has a shorter dimension in the front-rear direction than a dimension in a horizontal state where the upper surface becomes horizontal.Type: ApplicationFiled: July 19, 2022Publication date: January 26, 2023Applicant: Mazda Motor CorporationInventors: Yoshinori IKEDA, Tsutomu SHIBATA, Yosuke SAWADA, Tetsuya SHIMOMURA
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Patent number: 10886547Abstract: A fuel cell system includes: a fuel cell including a fuel gas passage through which a fuel gas flows and an oxidant gas passage through which an oxidant gas flows, an inlet of the fuel gas passage being located closer to an outlet of the oxidant gas passage than to an inlet of the oxidant gas passage, an outlet of the fuel gas passage being located closer to the inlet of the oxidant gas passage than to the outlet of the oxidant gas passage; an oxidant gas supply unit supplying the oxidant gas to the fuel cell; and a supply amount controller configured to control the oxidant gas supply unit, the supply amount controller is configured to control the oxidant gas supply unit so that a stoichiometric ratio of the oxidant gas in a high-temperature high output power state is greater than that in a high-temperature low output power state.Type: GrantFiled: February 8, 2019Date of Patent: January 5, 2021Assignee: Toyota Jidosha Kabushiki KaishaInventors: Tetsuya Shimomura, Masashi Maeda, Norimitsu Takeuchi
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Publication number: 20190252704Abstract: A fuel cell system includes: a fuel cell including a fuel gas passage through which a fuel gas flows and an oxidant gas passage through which an oxidant gas flows, an inlet of the fuel gas passage being located closer to an outlet of the oxidant gas passage than to an inlet of the oxidant gas passage, an outlet of the fuel gas passage being located closer to the inlet of the oxidant gas passage than to the outlet of the oxidant gas passage; an oxidant gas supply unit supplying the oxidant gas to the fuel cell; and a supply amount controller configured to control the oxidant gas supply unit, the supply amount controller is configured to control the oxidant gas supply unit so that a stoichiometric ratio of the oxidant gas in a high-temperature high output power state is greater than that in a high-temperature low output power state.Type: ApplicationFiled: February 8, 2019Publication date: August 15, 2019Applicant: Toyota Jidosha Kabushiki KaishaInventors: Tetsuya Shimomura, Masashi Maeda, Norimitsu Takeuchi
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Patent number: 10373757Abstract: A printed circuit board according to an embodiment of the present invention includes, alternately, at least one insulating layer containing a synthetic resin as a main component; and a plurality of conductive layers including circuit patterns, wherein the plurality of circuit patterns of the plurality of conductive layers form a spiral pattern in plan view, and the plurality of circuit patterns are connected together via a plurality of through-holes so as to form a single closed loop in which a current flows counterclockwise or clockwise in an entirety of the spiral pattern. The conductive layers are preferably formed on both surfaces of the at least one insulating layer so as to form a pair.Type: GrantFiled: July 1, 2015Date of Patent: August 6, 2019Assignee: SUMITOMO ELECTRIC PRINTED CIRCUITS, INC.Inventors: Masahiko Kouchi, Tetsuya Shimomura
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Patent number: 9771643Abstract: The invention provides a carburized part which has excellent medium-cycle fatigue strength in particular subjected to surface-hardening treatment by carburization. The invention provides a carburized part including a carburized layer formed by performing carburizing treatment to a steel, the steel including, in terms of % by mass: 0.15% to 0.25% of C, 0.15% or less of Si, 0.4% to 1.1% of Mn, 0.8% to 1.4% of Cr, 0.25% to 0.55% of Mo, 0.015% or less of P, and 0.035% or less of S, with the remainder being Fe and unavoidable impurities, and the steel satisfying the following relation; 0.10?[Mo]/(10[Si]+[Mn]+[Cr])?0.40, in which [M] represents a content of element M in terms of % by mass.Type: GrantFiled: April 4, 2014Date of Patent: September 26, 2017Assignees: HONDA MOTOR CO., LTD., DAIDO STEEL CO., LTD.Inventors: Akihito Ninomiya, Yoshinari Okada, Takahiro Miyazaki, Yasushi Matsumura, Shinichiro Kato, Tetsuya Shimomura
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Publication number: 20170133152Abstract: A printed circuit board according to an embodiment of the present invention includes, alternately, at least one insulating layer containing a synthetic resin as a main component; and a plurality of conductive layers including circuit patterns, wherein the plurality of circuit patterns of the plurality of conductive layers form a spiral pattern in plan view, and the plurality of circuit patterns are connected together via a plurality of through-holes so as to form a single closed loop in which a current flows counterclockwise or clockwise in an entirety of the spiral pattern. The conductive layers are preferably formed on both surfaces of the at least one insulating layer so as to form a pair.Type: ApplicationFiled: July 1, 2015Publication date: May 11, 2017Applicant: SUMITOMO ELECTRIC PRINTED CIRCUITS, INC.Inventors: Masahiko KOUCHI, Tetsuya SHIMOMURA
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Patent number: 8866027Abstract: The printed wiring board 1 includes the metallic substrate 2, the insulating layer 3 provided on the surface of the metallic substrate 2, and the conductive layer 4 formed on the surface of the insulating layer 3. The conductive layer 4 is electrically connected to the metallic substrate 2. A bottomed via hole or a through hole 6 is formed in the insulating layer 3 and the conducive layer 4. The via hole has a bottom in the metallic substrate 2, and has a wall surface in the insulating layer 3 and in the conductive layer 4. The through hole 6 extends through the insulating layer 3, the conductive layer 4, and the metallic substrate 2. Conductive paste 7 fills the bottomed via hole or the through hole 6 to electrically connect the metallic substrate 2 and the conductive layer 4 with each other. The printed wiring board 1 is subjected to a process in which current is applied to the interface between the metallic substrate 2 and the conductive paste 7.Type: GrantFiled: January 16, 2008Date of Patent: October 21, 2014Assignees: Sumitomo Electric Industries, Ltd., Sumitomo Electric Printed Circuits, Inc.Inventors: Yoshio Oka, Jinjoo Park, Kazuyuki Maeda, Narito Yagi, Tetsuya Shimomura, Junichiro Nishikawa
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Publication number: 20140299234Abstract: The invention provides a carburized part which has excellent medium-cycle fatigue strength in particular subjected to surface-hardening treatment by carburization. The invention provides a carburized part including a carburized layer formed by performing carburizing treatment to a steel, the steel including, in terms of % by mass: 0.15% to 0.25% of C, 0.15% or less of Si, 0.4% to 1.1% of Mn, 0.8% to 1.4% of Cr, 0.25% to 0.55% of Mo, 0.015% or less of P, and 0.035% or less of S, with the remainder being Fe and unavoidable impurities, and the steel satisfying the following relation; 0.10?[Mo]/(10[Si]+[Mn]+[Cr])?0.40, in which [M] represents a content of element M in terms of % by mass.Type: ApplicationFiled: April 4, 2014Publication date: October 9, 2014Applicants: HONDA MOTOR CO., LTD., DAIDO STEEL CO., LTD.Inventors: Shinichiro KATO, Takahiro MIYAZAKI, Yoshinari OKADA, Akihito NINOMIYA, Tetsuya SHIMOMURA, Yasushi MATSUMURA
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Publication number: 20100044094Abstract: The printed wiring board 1 includes the metallic substrate 2, the insulating layer 3 provided on the surface of the metallic substrate 2, and the conductive layer 4 formed on the surface of the insulating layer 3. The conductive layer 4 is electrically connected to the metallic substrate 2. A bottomed via hole or a through hole 6 is formed in the insulating layer 3 and the conducive layer 4. The via hole has a bottom in the metallic substrate 2, and has a wall surface in the insulating layer 3 and in the conductive layer 4. The through hole 6 extends through the insulating layer 3, the conductive layer 4, and the metallic substrate 2. Conductive paste 7 fills the bottomed via hole or the through hole 6 to electrically connect the metallic substrate 2 and the conductive layer 4 with each other. The printed wiring board 1 is subjected to a process in which current is applied to the interface between the metallic substrate 2 and the conductive paste 7.Type: ApplicationFiled: January 16, 2008Publication date: February 25, 2010Applicants: SUMITOMO ELECTRIC INDUSTRIES, LTD., SUMITOMO ELECTRIC PRINTED CIRCUITS, INC.Inventors: Yoshio Oka, Jinjoo Park, Kazuyuki Maeda, Narito Yagi, Tetsuya Shimomura, Junichiro Nishikawa
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Patent number: 7557809Abstract: The basic section of the multimedia data-processing system includes a CPU 1100, an image display unit 2100, a unified memory 1200, a system bus 1920, and devices 1300, 1400, and 1500 connected to the system bus. In this configuration, the CPU is formed on an LSI mounted on a single silicon wafer including instruction processing unit 1110 and display control unit 1140. Main storage area 1210 and display area 1220 are stored within the unified memory. Unified memory port 1910 for connecting the corresponding LSI and the unified memory is provided independently of the system bus intended to connect the LSI and the input/output devices. The unified memory port can be driven faster than system bus.Type: GrantFiled: November 9, 2004Date of Patent: July 7, 2009Assignee: Renesas Technology Corp.Inventors: Yasuhiro Nakatsuka, Tetsuya Shimomura, Manabu Jyou, Yuichiro Morita, Takashi Hotta, Kazushige Yamagishi, Yutaka Okada
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Patent number: 7333116Abstract: In order to reduce degradation of the processing performance of the data processor due to use of a part of the main memory as a display frame buffer, when an access request to the memory 200 is generated from the CPU 310, the memory controller 400 holds it once, requests the display controller 560 to stop the access to the memory 200 which is in execution, when data to the access executed already is transferred from the memory 200, holds it, and transfers the access request from the CPU bus 310 which is held by the memory 200. When the access from the CPU bus 310 ends, the memory controller 400 restarts the access stopped in the display controller 560 and passes the held data to the display controller 560.Type: GrantFiled: July 18, 2005Date of Patent: February 19, 2008Assignee: Renesas Technology CorporationInventors: Tetsuya Shimomura, Shigeru Matsuo, Koyo Katsura, Tatsuki Inuzuka, Yasuhiro Nakatsuka
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Publication number: 20050264574Abstract: In order to reduce degradation of the processing performance of the data processor due to use of a part of the main memory as a display frame buffer, when an access request to the memory 200 is generated from the CPU 310, the memory controller 400 holds it once, requests the display controller 560 to stop the access to the memory 200 which is in execution, when data to the access executed already is transferred from the memory 200, holds it, and transfers the access request from the CPU bus 310 which is held by the memory 200. When the access from the CPU bus 310 ends, the memory controller 400 restarts the access stopped in the display controller 560 and passes the held data to the display controller 560.Type: ApplicationFiled: July 18, 2005Publication date: December 1, 2005Inventors: Tetsuya Shimomura, Shigeru Matsuo, Koyo Katsura, Tatsuki Inuzuka, Yasuhiro Nakatsuka
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Patent number: 6954206Abstract: In order to reduce degradation of the processing performance of the data processor due to use of a part of the main memory as a display frame buffer, when an access request to the memory 200 is generated from the CPU 310, the memory controller 400 holds it once, requests the display controller 560 to stop the access to the memory 200 which is in execution, when data to the access executed already is transferred from the memory 200, holds it, and transfers the access request from the CPU bus 310 which is held by the memory 200. When the access from the CPU bus 310 ends, the memory controller 400 restarts the access stopped in the display controller 560 and passes the held data to the display controller 560.Type: GrantFiled: September 25, 2003Date of Patent: October 11, 2005Assignee: Hitachi, Ltd.Inventors: Tetsuya Shimomura, Shigeru Matsuo, Koyo Katsura, Tatsuki Inuzuka, Yasuhiro Nakatsuka
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Publication number: 20050062749Abstract: The basic section of the multimedia data-processing system includes a CPU 1100, an image display unit 2100, a unified memory 1200, a system bus 1920, and devices 1300, 1400, and 1500 connected to the system bus. In this configuration, the CPU is formed on an LSI mounted on a single silicon wafer including instruction processing unit 1110 and display control unit 1140. Main storage area 1210 and display area 1220 are stored within the unified memory. Unified memory port 1910 for connecting the corresponding LSI and the unified memory is provided independently of the system bus intended to connect the LSI and the input/output devices. The unified memory port can be driven faster than system bus.Type: ApplicationFiled: November 9, 2004Publication date: March 24, 2005Inventors: Yasuhiro Nakatsuka, Tetsuya Shimomura, Manabu Jyou, Yuichiro Morita, Takashi Hotta, Kazushige Yamagishi, Yutaka Okada
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Patent number: 6839063Abstract: The basic section of the multimedia data-processing system includes a CPU 1100, an image display unit 2100, a unified memory 1200, a system bus 1920, and devices 1300, 1400, and 1500 connected to the system bus. In this configuration, the CPU is formed on an LSI mounted on a single silicon wafer including instruction processing unit 1110 and display control unit 1140. Main storage area 1210 and display area 1220 are stored within the unified memory. Unified memory port 1910 for connecting the corresponding LSI and the unified memory is provided independently of the system bus intended to connect the LSI and the input/output devices. The unified memory port can be driven faster than system bus.Type: GrantFiled: February 26, 2001Date of Patent: January 4, 2005Assignee: Renesas Technology Corp.Inventors: Yasuhiro Nakatsuka, Tetsuya Shimomura, Manabu Jyou, Yuichiro Morita, Takashi Hotta, Kazushige Yamagishi, Yutaka Okada
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Publication number: 20040193779Abstract: A memory controller includes a terminal to receive, from a processor, a request for access to a dynamic random access memory having a data storage area divided into a plurality of banks each divided into a plurality of pages. A memory control unit is also provided to activate a page to be accessed, based on said access request from said processor, and to execute, before a next request for access to a page to be accessed subsequently by said processor, precharge of said page to be accessed subsequently.Type: ApplicationFiled: April 15, 2004Publication date: September 30, 2004Inventors: Yuichiro Morita, Manabu Jyou, Yasuhiro Nakatsuka, Tetsuya Shimomura, Yutaka Okada, Kazushige Yamagishi
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Patent number: 6745279Abstract: A memory controller is disclosed, in which upon receipt of an access request from a device, the memory controller activates a page designated by a row address of a first bank at a predetermined memory cycle, based on the access request. After that, before the read access to a page of the first bank, a second bank next to be accessed is precharged. In the case where a page mishit occurs due to the access from the first bank to the second bank by the graphic processing after the access to the first bank by the read operation, the memory controller activates the second bank immediately without precharging.Type: GrantFiled: September 26, 2001Date of Patent: June 1, 2004Assignee: Hitachi, Ltd.Inventors: Yuichiro Morita, Manabu Jyou, Yasuhiro Nakatsuka, Tetsuya Shimomura, Yutaka Okada, Kazushige Yamagishi
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Patent number: 6717583Abstract: In order to reduce degradation of the processing performance of the data processor due to use of a part of the main memory as a display frame buffer, when an access request to the memory 200 is generated from the CPU 310, the memory controller 400 holds it once, requests the display controller 560 to stop the access to the memory 200 which is in execution, when data to the access executed already is transferred from the memory 200, holds it, and transfers the access request from the CPU bus 310 which is held by the memory 200. When the access from the CPU bus 310 ends, the memory controller 400 restarts the access stopped in the display controller 560 and passes the held data to the display controller 560.Type: GrantFiled: November 26, 2001Date of Patent: April 6, 2004Assignee: Hitachi, Ltd.Inventors: Tetsuya Shimomura, Shigeru Matsuo, Koyo Katsura, Tatsuki Inuzuka, Yasuhiro Nakatsuka
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Publication number: 20040056865Abstract: In order to reduce degradation of the processing performance of the data processor due to use of a part of the main memory as a display frame buffer, when an access request to the memory 200 is generated from the CPU 310, the memory controller 400 holds it once, requests the display controller 560 to stop the access to the memory 200 which is in execution, when data to the access executed already is transferred from the memory 200, holds it, and transfers the access request from the CPU bus 310 which is held by the memory 200. When the access from the CPU bus 310 ends, the memory controller 400 restarts the access stopped in the display controller 560 and passes the held data to the display controller 560.Type: ApplicationFiled: September 25, 2003Publication date: March 25, 2004Inventors: Tetsuya Shimomura, Shigeru Matsuo, Koyo Katsura, Tatsuki Inuzuka, Yasuhiro Nakatsuka
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Patent number: D716241Type: GrantFiled: December 18, 2013Date of Patent: October 28, 2014Assignees: Sumitomo Electric Printed Circuits, Inc., Sumitomo Electric Fine Polymer, Inc.Inventors: Masahiko Kouchi, Tetsuya Shimomura, Makoto Nakabayashi