Patents by Inventor Tetsuya Shimomura

Tetsuya Shimomura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230023059
    Abstract: A lower structure for a hybrid automobile in which a high-voltage battery is disposed in a lower surface of a floor panel includes an engine exhaust system component which is disposed in front of the high-voltage battery in the lower surface of the floor panel and on one vehicle-width-direction side of a center in a vehicle width direction and high-voltage devices which are disposed in front of the high-voltage battery and on another vehicle-width-direction side of the center in the vehicle width direction. In-vehicle equipment is disposed between the high-voltage battery and the high-voltage devices, and the in-vehicle equipment is in an inclined state where an upper surface of the in-vehicle equipment is inclined in a front-rear direction such that the in-vehicle equipment has a shorter dimension in the front-rear direction than a dimension in a horizontal state where the upper surface becomes horizontal.
    Type: Application
    Filed: July 19, 2022
    Publication date: January 26, 2023
    Applicant: Mazda Motor Corporation
    Inventors: Yoshinori IKEDA, Tsutomu SHIBATA, Yosuke SAWADA, Tetsuya SHIMOMURA
  • Patent number: 10886547
    Abstract: A fuel cell system includes: a fuel cell including a fuel gas passage through which a fuel gas flows and an oxidant gas passage through which an oxidant gas flows, an inlet of the fuel gas passage being located closer to an outlet of the oxidant gas passage than to an inlet of the oxidant gas passage, an outlet of the fuel gas passage being located closer to the inlet of the oxidant gas passage than to the outlet of the oxidant gas passage; an oxidant gas supply unit supplying the oxidant gas to the fuel cell; and a supply amount controller configured to control the oxidant gas supply unit, the supply amount controller is configured to control the oxidant gas supply unit so that a stoichiometric ratio of the oxidant gas in a high-temperature high output power state is greater than that in a high-temperature low output power state.
    Type: Grant
    Filed: February 8, 2019
    Date of Patent: January 5, 2021
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Tetsuya Shimomura, Masashi Maeda, Norimitsu Takeuchi
  • Publication number: 20190252704
    Abstract: A fuel cell system includes: a fuel cell including a fuel gas passage through which a fuel gas flows and an oxidant gas passage through which an oxidant gas flows, an inlet of the fuel gas passage being located closer to an outlet of the oxidant gas passage than to an inlet of the oxidant gas passage, an outlet of the fuel gas passage being located closer to the inlet of the oxidant gas passage than to the outlet of the oxidant gas passage; an oxidant gas supply unit supplying the oxidant gas to the fuel cell; and a supply amount controller configured to control the oxidant gas supply unit, the supply amount controller is configured to control the oxidant gas supply unit so that a stoichiometric ratio of the oxidant gas in a high-temperature high output power state is greater than that in a high-temperature low output power state.
    Type: Application
    Filed: February 8, 2019
    Publication date: August 15, 2019
    Applicant: Toyota Jidosha Kabushiki Kaisha
    Inventors: Tetsuya Shimomura, Masashi Maeda, Norimitsu Takeuchi
  • Patent number: 10373757
    Abstract: A printed circuit board according to an embodiment of the present invention includes, alternately, at least one insulating layer containing a synthetic resin as a main component; and a plurality of conductive layers including circuit patterns, wherein the plurality of circuit patterns of the plurality of conductive layers form a spiral pattern in plan view, and the plurality of circuit patterns are connected together via a plurality of through-holes so as to form a single closed loop in which a current flows counterclockwise or clockwise in an entirety of the spiral pattern. The conductive layers are preferably formed on both surfaces of the at least one insulating layer so as to form a pair.
    Type: Grant
    Filed: July 1, 2015
    Date of Patent: August 6, 2019
    Assignee: SUMITOMO ELECTRIC PRINTED CIRCUITS, INC.
    Inventors: Masahiko Kouchi, Tetsuya Shimomura
  • Patent number: 9771643
    Abstract: The invention provides a carburized part which has excellent medium-cycle fatigue strength in particular subjected to surface-hardening treatment by carburization. The invention provides a carburized part including a carburized layer formed by performing carburizing treatment to a steel, the steel including, in terms of % by mass: 0.15% to 0.25% of C, 0.15% or less of Si, 0.4% to 1.1% of Mn, 0.8% to 1.4% of Cr, 0.25% to 0.55% of Mo, 0.015% or less of P, and 0.035% or less of S, with the remainder being Fe and unavoidable impurities, and the steel satisfying the following relation; 0.10?[Mo]/(10[Si]+[Mn]+[Cr])?0.40, in which [M] represents a content of element M in terms of % by mass.
    Type: Grant
    Filed: April 4, 2014
    Date of Patent: September 26, 2017
    Assignees: HONDA MOTOR CO., LTD., DAIDO STEEL CO., LTD.
    Inventors: Akihito Ninomiya, Yoshinari Okada, Takahiro Miyazaki, Yasushi Matsumura, Shinichiro Kato, Tetsuya Shimomura
  • Publication number: 20170133152
    Abstract: A printed circuit board according to an embodiment of the present invention includes, alternately, at least one insulating layer containing a synthetic resin as a main component; and a plurality of conductive layers including circuit patterns, wherein the plurality of circuit patterns of the plurality of conductive layers form a spiral pattern in plan view, and the plurality of circuit patterns are connected together via a plurality of through-holes so as to form a single closed loop in which a current flows counterclockwise or clockwise in an entirety of the spiral pattern. The conductive layers are preferably formed on both surfaces of the at least one insulating layer so as to form a pair.
    Type: Application
    Filed: July 1, 2015
    Publication date: May 11, 2017
    Applicant: SUMITOMO ELECTRIC PRINTED CIRCUITS, INC.
    Inventors: Masahiko KOUCHI, Tetsuya SHIMOMURA
  • Patent number: 8866027
    Abstract: The printed wiring board 1 includes the metallic substrate 2, the insulating layer 3 provided on the surface of the metallic substrate 2, and the conductive layer 4 formed on the surface of the insulating layer 3. The conductive layer 4 is electrically connected to the metallic substrate 2. A bottomed via hole or a through hole 6 is formed in the insulating layer 3 and the conducive layer 4. The via hole has a bottom in the metallic substrate 2, and has a wall surface in the insulating layer 3 and in the conductive layer 4. The through hole 6 extends through the insulating layer 3, the conductive layer 4, and the metallic substrate 2. Conductive paste 7 fills the bottomed via hole or the through hole 6 to electrically connect the metallic substrate 2 and the conductive layer 4 with each other. The printed wiring board 1 is subjected to a process in which current is applied to the interface between the metallic substrate 2 and the conductive paste 7.
    Type: Grant
    Filed: January 16, 2008
    Date of Patent: October 21, 2014
    Assignees: Sumitomo Electric Industries, Ltd., Sumitomo Electric Printed Circuits, Inc.
    Inventors: Yoshio Oka, Jinjoo Park, Kazuyuki Maeda, Narito Yagi, Tetsuya Shimomura, Junichiro Nishikawa
  • Publication number: 20140299234
    Abstract: The invention provides a carburized part which has excellent medium-cycle fatigue strength in particular subjected to surface-hardening treatment by carburization. The invention provides a carburized part including a carburized layer formed by performing carburizing treatment to a steel, the steel including, in terms of % by mass: 0.15% to 0.25% of C, 0.15% or less of Si, 0.4% to 1.1% of Mn, 0.8% to 1.4% of Cr, 0.25% to 0.55% of Mo, 0.015% or less of P, and 0.035% or less of S, with the remainder being Fe and unavoidable impurities, and the steel satisfying the following relation; 0.10?[Mo]/(10[Si]+[Mn]+[Cr])?0.40, in which [M] represents a content of element M in terms of % by mass.
    Type: Application
    Filed: April 4, 2014
    Publication date: October 9, 2014
    Applicants: HONDA MOTOR CO., LTD., DAIDO STEEL CO., LTD.
    Inventors: Shinichiro KATO, Takahiro MIYAZAKI, Yoshinari OKADA, Akihito NINOMIYA, Tetsuya SHIMOMURA, Yasushi MATSUMURA
  • Publication number: 20100044094
    Abstract: The printed wiring board 1 includes the metallic substrate 2, the insulating layer 3 provided on the surface of the metallic substrate 2, and the conductive layer 4 formed on the surface of the insulating layer 3. The conductive layer 4 is electrically connected to the metallic substrate 2. A bottomed via hole or a through hole 6 is formed in the insulating layer 3 and the conducive layer 4. The via hole has a bottom in the metallic substrate 2, and has a wall surface in the insulating layer 3 and in the conductive layer 4. The through hole 6 extends through the insulating layer 3, the conductive layer 4, and the metallic substrate 2. Conductive paste 7 fills the bottomed via hole or the through hole 6 to electrically connect the metallic substrate 2 and the conductive layer 4 with each other. The printed wiring board 1 is subjected to a process in which current is applied to the interface between the metallic substrate 2 and the conductive paste 7.
    Type: Application
    Filed: January 16, 2008
    Publication date: February 25, 2010
    Applicants: SUMITOMO ELECTRIC INDUSTRIES, LTD., SUMITOMO ELECTRIC PRINTED CIRCUITS, INC.
    Inventors: Yoshio Oka, Jinjoo Park, Kazuyuki Maeda, Narito Yagi, Tetsuya Shimomura, Junichiro Nishikawa
  • Patent number: 7557809
    Abstract: The basic section of the multimedia data-processing system includes a CPU 1100, an image display unit 2100, a unified memory 1200, a system bus 1920, and devices 1300, 1400, and 1500 connected to the system bus. In this configuration, the CPU is formed on an LSI mounted on a single silicon wafer including instruction processing unit 1110 and display control unit 1140. Main storage area 1210 and display area 1220 are stored within the unified memory. Unified memory port 1910 for connecting the corresponding LSI and the unified memory is provided independently of the system bus intended to connect the LSI and the input/output devices. The unified memory port can be driven faster than system bus.
    Type: Grant
    Filed: November 9, 2004
    Date of Patent: July 7, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Yasuhiro Nakatsuka, Tetsuya Shimomura, Manabu Jyou, Yuichiro Morita, Takashi Hotta, Kazushige Yamagishi, Yutaka Okada
  • Patent number: 7333116
    Abstract: In order to reduce degradation of the processing performance of the data processor due to use of a part of the main memory as a display frame buffer, when an access request to the memory 200 is generated from the CPU 310, the memory controller 400 holds it once, requests the display controller 560 to stop the access to the memory 200 which is in execution, when data to the access executed already is transferred from the memory 200, holds it, and transfers the access request from the CPU bus 310 which is held by the memory 200. When the access from the CPU bus 310 ends, the memory controller 400 restarts the access stopped in the display controller 560 and passes the held data to the display controller 560.
    Type: Grant
    Filed: July 18, 2005
    Date of Patent: February 19, 2008
    Assignee: Renesas Technology Corporation
    Inventors: Tetsuya Shimomura, Shigeru Matsuo, Koyo Katsura, Tatsuki Inuzuka, Yasuhiro Nakatsuka
  • Publication number: 20050264574
    Abstract: In order to reduce degradation of the processing performance of the data processor due to use of a part of the main memory as a display frame buffer, when an access request to the memory 200 is generated from the CPU 310, the memory controller 400 holds it once, requests the display controller 560 to stop the access to the memory 200 which is in execution, when data to the access executed already is transferred from the memory 200, holds it, and transfers the access request from the CPU bus 310 which is held by the memory 200. When the access from the CPU bus 310 ends, the memory controller 400 restarts the access stopped in the display controller 560 and passes the held data to the display controller 560.
    Type: Application
    Filed: July 18, 2005
    Publication date: December 1, 2005
    Inventors: Tetsuya Shimomura, Shigeru Matsuo, Koyo Katsura, Tatsuki Inuzuka, Yasuhiro Nakatsuka
  • Patent number: 6954206
    Abstract: In order to reduce degradation of the processing performance of the data processor due to use of a part of the main memory as a display frame buffer, when an access request to the memory 200 is generated from the CPU 310, the memory controller 400 holds it once, requests the display controller 560 to stop the access to the memory 200 which is in execution, when data to the access executed already is transferred from the memory 200, holds it, and transfers the access request from the CPU bus 310 which is held by the memory 200. When the access from the CPU bus 310 ends, the memory controller 400 restarts the access stopped in the display controller 560 and passes the held data to the display controller 560.
    Type: Grant
    Filed: September 25, 2003
    Date of Patent: October 11, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Tetsuya Shimomura, Shigeru Matsuo, Koyo Katsura, Tatsuki Inuzuka, Yasuhiro Nakatsuka
  • Publication number: 20050062749
    Abstract: The basic section of the multimedia data-processing system includes a CPU 1100, an image display unit 2100, a unified memory 1200, a system bus 1920, and devices 1300, 1400, and 1500 connected to the system bus. In this configuration, the CPU is formed on an LSI mounted on a single silicon wafer including instruction processing unit 1110 and display control unit 1140. Main storage area 1210 and display area 1220 are stored within the unified memory. Unified memory port 1910 for connecting the corresponding LSI and the unified memory is provided independently of the system bus intended to connect the LSI and the input/output devices. The unified memory port can be driven faster than system bus.
    Type: Application
    Filed: November 9, 2004
    Publication date: March 24, 2005
    Inventors: Yasuhiro Nakatsuka, Tetsuya Shimomura, Manabu Jyou, Yuichiro Morita, Takashi Hotta, Kazushige Yamagishi, Yutaka Okada
  • Patent number: 6839063
    Abstract: The basic section of the multimedia data-processing system includes a CPU 1100, an image display unit 2100, a unified memory 1200, a system bus 1920, and devices 1300, 1400, and 1500 connected to the system bus. In this configuration, the CPU is formed on an LSI mounted on a single silicon wafer including instruction processing unit 1110 and display control unit 1140. Main storage area 1210 and display area 1220 are stored within the unified memory. Unified memory port 1910 for connecting the corresponding LSI and the unified memory is provided independently of the system bus intended to connect the LSI and the input/output devices. The unified memory port can be driven faster than system bus.
    Type: Grant
    Filed: February 26, 2001
    Date of Patent: January 4, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Yasuhiro Nakatsuka, Tetsuya Shimomura, Manabu Jyou, Yuichiro Morita, Takashi Hotta, Kazushige Yamagishi, Yutaka Okada
  • Publication number: 20040193779
    Abstract: A memory controller includes a terminal to receive, from a processor, a request for access to a dynamic random access memory having a data storage area divided into a plurality of banks each divided into a plurality of pages. A memory control unit is also provided to activate a page to be accessed, based on said access request from said processor, and to execute, before a next request for access to a page to be accessed subsequently by said processor, precharge of said page to be accessed subsequently.
    Type: Application
    Filed: April 15, 2004
    Publication date: September 30, 2004
    Inventors: Yuichiro Morita, Manabu Jyou, Yasuhiro Nakatsuka, Tetsuya Shimomura, Yutaka Okada, Kazushige Yamagishi
  • Patent number: 6745279
    Abstract: A memory controller is disclosed, in which upon receipt of an access request from a device, the memory controller activates a page designated by a row address of a first bank at a predetermined memory cycle, based on the access request. After that, before the read access to a page of the first bank, a second bank next to be accessed is precharged. In the case where a page mishit occurs due to the access from the first bank to the second bank by the graphic processing after the access to the first bank by the read operation, the memory controller activates the second bank immediately without precharging.
    Type: Grant
    Filed: September 26, 2001
    Date of Patent: June 1, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Yuichiro Morita, Manabu Jyou, Yasuhiro Nakatsuka, Tetsuya Shimomura, Yutaka Okada, Kazushige Yamagishi
  • Patent number: 6717583
    Abstract: In order to reduce degradation of the processing performance of the data processor due to use of a part of the main memory as a display frame buffer, when an access request to the memory 200 is generated from the CPU 310, the memory controller 400 holds it once, requests the display controller 560 to stop the access to the memory 200 which is in execution, when data to the access executed already is transferred from the memory 200, holds it, and transfers the access request from the CPU bus 310 which is held by the memory 200. When the access from the CPU bus 310 ends, the memory controller 400 restarts the access stopped in the display controller 560 and passes the held data to the display controller 560.
    Type: Grant
    Filed: November 26, 2001
    Date of Patent: April 6, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Tetsuya Shimomura, Shigeru Matsuo, Koyo Katsura, Tatsuki Inuzuka, Yasuhiro Nakatsuka
  • Publication number: 20040056865
    Abstract: In order to reduce degradation of the processing performance of the data processor due to use of a part of the main memory as a display frame buffer, when an access request to the memory 200 is generated from the CPU 310, the memory controller 400 holds it once, requests the display controller 560 to stop the access to the memory 200 which is in execution, when data to the access executed already is transferred from the memory 200, holds it, and transfers the access request from the CPU bus 310 which is held by the memory 200. When the access from the CPU bus 310 ends, the memory controller 400 restarts the access stopped in the display controller 560 and passes the held data to the display controller 560.
    Type: Application
    Filed: September 25, 2003
    Publication date: March 25, 2004
    Inventors: Tetsuya Shimomura, Shigeru Matsuo, Koyo Katsura, Tatsuki Inuzuka, Yasuhiro Nakatsuka
  • Patent number: D716241
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: October 28, 2014
    Assignees: Sumitomo Electric Printed Circuits, Inc., Sumitomo Electric Fine Polymer, Inc.
    Inventors: Masahiko Kouchi, Tetsuya Shimomura, Makoto Nakabayashi