Patents by Inventor Tetsuya Takeuchi

Tetsuya Takeuchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10411438
    Abstract: Provided is a semiconductor multilayer film reflecting mirror formed by alternately repeating a first nitride film containing In (indium) and a second nitride film not containing In. The reflecting mirror includes an inter-film transition layer between the first and second nitride films, the composition of which is varied from the composition of the first nitride film to the composition of the second nitride film. The inter-film transition layer has a first transition layer formed on the first nitride film and containing In and Al (aluminum), and a second transition layer formed on the first transition layer and containing Al but not containing In. In the first transition layer, the percentages of In and Al are decreased from the first nitride film to the second transition layer, and the percentage of In in the first transition layer starts to decrease at a same or closer position to the first nitride film than the percentage of Al.
    Type: Grant
    Filed: December 8, 2017
    Date of Patent: September 10, 2019
    Assignees: STANLEY ELECTRIC CO., LTD., MEIJO UNIVERSITY
    Inventors: Tetsuya Takeuchi, Isamu Akasaki, Takanobu Akagi
  • Publication number: 20190148592
    Abstract: To provide a Group III nitride semiconductor light-emitting device exhibiting the improved light extraction efficiency as well as reducing the influence of polarization that a p-type conductivity portion and an n-type conductivity portion occur in the AlGaN layer caused by the Al composition variation, and a production method therefor. A first p-type contact layer is a p-type AlGaN layer. A second p-type contact layer is a p-type AlGaN layer. The Al composition in the first p-type contact layer is reduced with distance from a light-emitting layer. The Al composition in the second p-type contact layer is reduced with distance from the light-emitting layer. The Al composition in the second p-type contact layer is lower than that in the first p-type contact layer. The Al composition variation rate to the unit thickness in the second p-type contact layer is higher than that in the first p-type contact layer.
    Type: Application
    Filed: November 8, 2018
    Publication date: May 16, 2019
    Inventors: Tetsuya TAKEUCHI, Satoshi KAMIYAMA, Motoaki IWAYA, Isamu AKASAKI, Hisanori KOJIMA, Toshiki YASUDA, Kazuyoshi IIDA
  • Patent number: 10116120
    Abstract: A semiconductor multilayer film mirror is configured such that a pair of an InAlN-based semiconductor film and a GaN-based semiconductor film is layered a plurality of times in a cyclic fashion and the InAlN-based semiconductor film has an In composition of less than 18 at %. The semiconductor multilayer film mirror includes a thin GaN cap layer formed on the InAlN-based semiconductor film and an AlGaN layer formed on the thin GaN cap layer between each pair of the InAlN-based semiconductor film and the GaN-based semiconductor film.
    Type: Grant
    Filed: December 8, 2017
    Date of Patent: October 30, 2018
    Assignees: STANLEY ELECTRIC CO., LTD., MEIJO UNIVERSITY
    Inventors: Tetsuya Takeuchi, Isamu Akasaki, Shinichi Tanaka, Kazufumi Tanaka
  • Publication number: 20180166856
    Abstract: A semiconductor multilayer film mirror is configured such that a pair of an InAlN-based semiconductor film and a GaN-based semiconductor film is layered a plurality of times in a cyclic fashion and the InAlN-based semiconductor film has an In composition of less than 18 at %. The semiconductor multilayer film mirror includes a thin GaN cap layer formed on the InAlN-based semiconductor film and an AlGaN layer formed on the thin GaN cap layer between each pair of the InAlN-based semiconductor film and the GaN-based semiconductor film.
    Type: Application
    Filed: December 8, 2017
    Publication date: June 14, 2018
    Applicants: MEIJO UNIVERSITY, STANLEY ELECTRIC CO., LTD.
    Inventors: Tetsuya TAKEUCHI, Isamu AKASAKI, Shinichi TANAKA, Kazufumi TANAKA
  • Publication number: 20180166855
    Abstract: Provided is a semiconductor multilayer film reflecting mirror formed by alternately repeating a first nitride film containing In (indium) and a second nitride film not containing In. The reflecting mirror includes an inter-film transition layer between the first and second nitride films, the composition of which is varied from the composition of the first nitride film to the composition of the second nitride film. The inter-film transition layer has a first transition layer formed on the first nitride film and containing In and Al (aluminum), and a second transition layer formed on the first transition layer and containing Al but not containing In. In the first transition layer, the percentages of In and Al are decreased from the first nitride film to the second transition layer, and the percentage of In in the first transition layer starts to decrease at a same or closer position to the first nitride film than the percentage of Al.
    Type: Application
    Filed: December 8, 2017
    Publication date: June 14, 2018
    Applicants: MEIJO UNIVERSITY, STANLEY ELECTRIC CO., LTD.
    Inventors: Tetsuya TAKEUCHI, Isamu AKASAKI, Takanobu AKAGI
  • Patent number: 9847449
    Abstract: A nitride semiconductor light-emitting device with periodic gain active layers includes an n-type semiconductor layer, a p-type semiconductor layer and a resonator. The device further includes a plurality of active layers disposed between the n-type and p-type semiconductor layers so as to correspond to a peak intensity position of light existing in the resonator and at least one interlayer disposed between the active layers. The active layer disposed at the p-type semiconductor layer side has a larger light emission intensity than the active layer disposed at the n-type semiconductor layer side.
    Type: Grant
    Filed: December 1, 2015
    Date of Patent: December 19, 2017
    Assignees: MEIJO UNIVERSITY, STANLEY ELECTRIC CO., LTD.
    Inventors: Kenjo Matsui, Tetsuya Takeuchi, Motoaki Iwaya, Isamu Akasaki, Takanobu Akagi, Sho Iwayama
  • Patent number: 9716209
    Abstract: This application provides a method of manufacturing an n-p-n nitride-semiconductor light-emitting device which includes a current confinement region (A) using a buried tunnel junction layer and in which a favorable luminous efficacy can be obtained and to provide the n-p-n nitride-semiconductor light-emitting device. The p-type activation of a p-type GaN crystal layer stacked below a tunnel junction layer is performed in an intermediate phase of a manufacturing process in which the p-type GaN crystal layer is exposed to atmosphere gas with the tunnel junction layer partially removed, before the tunnel junction layer is buried in an n-type GaN crystal layer. In the intermediate phase of the manufacturing process in which the p-type GaN crystal layer is exposed, p-type activation is efficiently performed on the p-type GaN crystal layer, and a p-type GaN crystal layer with low electric resistance can be obtained.
    Type: Grant
    Filed: August 23, 2016
    Date of Patent: July 25, 2017
    Assignee: MELIO UNIVERSITY
    Inventors: Tetsuya Takeuchi, Yuka Kuwano, Motoaki Iwaya, Isamu Akasaki
  • Publication number: 20170155016
    Abstract: Fabricating a high-quality nitride semiconductor crystal at a lower temperature. A nitride semiconductor crystal is fabricated by supplying onto a substrate (105) a group III element and/or a compound thereof, a nitrogen element and/or a compound thereof and an Sb element and/or a compound thereof, all of which serve as materials, and thereby vapor-growing at least one layer of nitride semiconductor film (104). A supply ratio of the Sb element to the nitrogen element in a growth process of the at least one layer of the nitride semiconductor film (104) is set to not less than 0.004.
    Type: Application
    Filed: March 4, 2014
    Publication date: June 1, 2017
    Applicant: MEIJO UNIVERSITY
    Inventors: Tetsuya TAKEUCHI, Tomoyuki SUZUKI, Hiroki SASAJIMA, Motoaki IWAYA, Isamu AKASAKI
  • Patent number: 9666753
    Abstract: A nitride semiconductor light emitting device includes a substrate as a base and an n-type semiconductor layer grown on a surface side of the substrate. Antimony (Sb) is added to the n-type semiconductor layer so that a molar fraction is not less than 0.1% and is less than 1%. A concentration of an n-type impurity in the n-type semiconductor layer is lower than an electron concentration.
    Type: Grant
    Filed: April 8, 2016
    Date of Patent: May 30, 2017
    Assignee: MEIJO UNIVERSITY
    Inventors: Tetsuya Takeuchi, Daisuke Komori, Kaku Takarabe, Motoaki Iwaya, Isamu Akasaki
  • Publication number: 20160365479
    Abstract: This application provides a method of manufacturing an n-p-n nitride-semiconductor light-emitting device which includes a current confinement region(A) using a buried tunnel junction layer and in which a favorable luminous efficacy can be obtained and to provide the n-p-n nitride-semiconductor light-emitting device. The p-type activation of a p-type GaN crystal layer stacked below a tunnel junction layer is performed in an intermediate phase of a manufacturing process in which the p-type GaN crystal layer is exposed to atmosphere gas with the tunnel junction layer partially removed, before the tunnel junction layer is buried in an n-type GaN crystal layer . In the intermediate phase of the manufacturing process in which the p-type GaN crystal layer is exposed, p-type activation is efficiently performed on the p-type GaN crystal layer , and a p-type GaN crystal layer with low electric resistance can be obtained.
    Type: Application
    Filed: August 23, 2016
    Publication date: December 15, 2016
    Applicant: MEIJO UNIVERSITY
    Inventors: Tetsuya TAKEUCHI, Yuka KUWANO, Motoaki IWAYA, Isamu AKASAKI
  • Publication number: 20160308094
    Abstract: A nitride semiconductor light emitting device includes a substrate as a base and an n-type semiconductor layer grown on a surface side of the substrate. In the device, antimony (Sb) is added to the n-type semiconductor layer so that a molar fraction is not less than 0.1%. The n-type semiconductor layer has an electron concentration of not less than 1×1018 cm?3.
    Type: Application
    Filed: April 8, 2016
    Publication date: October 20, 2016
    Applicant: MEIJO UNIVERSITY
    Inventors: Tetsuya TAKEUCHI, Daisuke KOMORI, Kaku TAKARABE, Motoaki IWAYA, Isamu AKASAKI
  • Patent number: 9470940
    Abstract: A semiconductor device includes a first electrode layer and a second electrode layer disposed over a substrate, a first insulating layer disposed over the first electrode layer, and a reflective electrode layer disposed on the first insulating layer and electrically connected to the first electrode layer, wherein the second electrode layer is exposed externally, and a thickness of the second electrode layer is greater than a thickness of the reflective electrode layer.
    Type: Grant
    Filed: October 17, 2014
    Date of Patent: October 18, 2016
    Assignee: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Tomiyasu Saito, Tatsuya Mise, Yoshio Matsuzawa, Tetsuya Takeuchi
  • Patent number: 9437775
    Abstract: An object is to improve a positive hole injection efficiency into an active layer in a nitride semiconductor light-emitting device. The nitride semiconductor light-emitting device is formed by stacking nitride semiconductor crystals each of which contains Al and has a polar or semipolar surface either serving as a growth face. The device includes an active layer (103), and first and second composition-graded layers (102, 104). The active layer (103) is interposed between the first and second composition-graded layers (102, 104). Each one of the first and second composition-graded layers is composition-graded so that an Al composition value is rendered smaller as each one of the first and second composition-graded layers (102, 104) comes close to a side where a sum of spontaneous polarization and piezoelectric polarization is negative.
    Type: Grant
    Filed: June 16, 2014
    Date of Patent: September 6, 2016
    Assignee: MEIJO UNIVERSITY
    Inventors: Tetsuya Takeuchi, Motoaki Iwaya, Isamu Akasaki
  • Publication number: 20160163919
    Abstract: A nitride semiconductor light-emitting device with periodic gain active layers includes an n-type semiconductor layer, a p-type semiconductor layer and a resonator. The device further includes a plurality of active layers disposed between the n-type and p-type semiconductor layers so as to correspond to a peak intensity position of light existing in the resonator and at least one interlayer disposed between the active layers. The active layer disposed at the p-type semiconductor layer side has a larger light emission intensity than the active layer disposed at the n-type semiconductor layer side.
    Type: Application
    Filed: December 1, 2015
    Publication date: June 9, 2016
    Applicants: MEIJO UNIVERSITY, STANLEY ELECTRIC CO., LTD.
    Inventors: Kenjo MATSUI, Tetsuya TAKEUCHI, Motoaki IWAYA, Isamu AKASAKI, Takanobu AKAGI, Sho IWAYAMA
  • Publication number: 20160149078
    Abstract: An object is to improve a positive hole injection efficiency into an active layer in a nitride semiconductor light-emitting device. The nitride semiconductor light-emitting device is formed by stacking nitride semiconductor crystals each of which contains Al and has a polar or semipolar surface either serving as a growth face. The device includes an active layer (103), and first and second composition-graded layers (102, 104). The active layer (103) is interposed between the first and second composition-graded layers (102, 104). Each one of the first and second composition-graded layers is composition-graded so that an Al composition value is rendered smaller as each one of the first and second composition-graded layers (102, 104) comes close to a side where a sum of spontaneous polarization and piezoelectric polarization is negative.
    Type: Application
    Filed: June 16, 2014
    Publication date: May 26, 2016
    Applicant: MEIJO UNIVERSITY
    Inventors: Tetsuya TAKEUCHI, Motoaki IWAYA, Isamu AKASAKI
  • Publication number: 20160056333
    Abstract: Achieving resistance reduction of a nitride semiconductor multilayer film reflector. In the nitride semiconductor multilayer film reflector, a first semiconductor layer (104) has a higher Al composition than a second semiconductor layer (106). A first composition-graded layer (105) is interposed between the first and second semiconductor layers (104, 106) so as to be located at a group III element face side of the first semiconductor layer (104), the first composition-graded layer (105) being adjusted so that its Al composition becomes lower as coming close to the second semiconductor layer (106). A second composition-graded layer (103) is interposed between the first and second semiconductor layers (104, 106) so as to be located at a nitride face side of the first semiconductor layer (104). The second composition-graded layer (103) is adjusted so that its Al composition becomes lower as coming close to the second semiconductor layer (106).
    Type: Application
    Filed: March 19, 2014
    Publication date: February 25, 2016
    Applicant: MEIJO UNIVERSITY
    Inventors: Tetsuya TAKEUCHI, Motoaki IWAYA, Isamu AKASAKI
  • Publication number: 20160020359
    Abstract: Fabricating a high-quality nitride semiconductor crystal at a lower temperature. A nitride semiconductor crystal is fabricated by supplying onto a substrate (105) a group III element and/or a compound thereof, a nitrogen element and/or a compound thereof and an Sb element and/or a compound thereof, all of which serve as materials, and thereby vapor-growing at least one layer of nitride semiconductor film (104). A supply ratio of the Sb element to the nitrogen element in a growth process of the at least one layer of the nitride semiconductor film (104) is set to not less than 0.004.
    Type: Application
    Filed: March 4, 2014
    Publication date: January 21, 2016
    Applicant: MEIJO UNIVERSITY
    Inventors: Tetsuya TAKEUCHI, Tomoyuki SUZUKI, Hiroki SASAJIMA, Motoaki IWAYA, Isamu AKASAKI
  • Publication number: 20150190989
    Abstract: Disclosed is a transparent laminate film that can relax stress applied by a squeegee during attachment of the film, and is protected from deterioration by salt-water corrosion, as well as has excellent solar-radiation shielding property, transparency, thermal insulation property, and scratch resistance. The transparent laminate film has a transparent polymer film; a transparent multilayer placed above the transparent polymer film, the transparent multilayer having one or more metal oxide layers and one or more metal layers laminated alternately; a pressure-sensitive adhesive layer placed above and in contact with the transparent multilayer; a polyolefin layer placed above and in contact with the pressure-sensitive adhesive layer; and a cured resin layer placed above the polyolefin layer.
    Type: Application
    Filed: March 18, 2015
    Publication date: July 9, 2015
    Applicant: SUMITOMO RIKO COMPANY LIMITED
    Inventors: Masataka INUDUKA, Tetsuji NARASAKI, Shoichi IKENO, Masafumi HIROSE, Motonori USHIO, Tetsuya TAKEUCHI
  • Publication number: 20150160499
    Abstract: A semiconductor device includes a first electrode layer and a second electrode layer disposed over a substrate, a first insulating layer disposed over the first electrode layer, and a reflective electrode layer disposed on the first insulating layer and electrically connected to the first electrode layer, wherein the second electrode layer is exposed externally, and a thickness of the second electrode layer is greater than a thickness of the reflective electrode layer.
    Type: Application
    Filed: October 17, 2014
    Publication date: June 11, 2015
    Inventors: Tomiyasu Saito, Tatsuya Mise, Yoshio Matsuzawa, Tetsuya Takeuchi
  • Patent number: 8901743
    Abstract: A method of fabricating a semiconductor device includes forming a first insulation film over a semiconductor substrate, the semiconductor substrate including an outer region and an inner region located at an inner side of the outer region, forming a first wiring over the first insulation film in the inner region, forming a second insulation film over the first wiring and over the first insulation film, decreasing a film thickness of the second insulation film in the inner region with regard to a film thickness of the second insulation film in the outer region, and polishing the second insulation film after the decreasing of the film thickness of the second insulation film.
    Type: Grant
    Filed: January 8, 2013
    Date of Patent: December 2, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Tomiyasu Saito, Tatsuya Mise, Hiromichi Ichikawa, Tetsuya Takeuchi, Genshi Okuda