Patents by Inventor Tezaswi Raja
Tezaswi Raja has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240104252Abstract: Techniques are described for detecting an electromagnetic (“EM”) fault injection attack directed toward circuitry in a target digital system. In various embodiments, a first node may be coupled to first driving circuitry, and a second node may be coupled to second driving circuitry. The driving circuitry is implemented in a manner such that a logic state on the second node has greater sensitivity to an EM pulse than has a logic state on the first node. Comparison circuitry may be coupled to the first and to the second nodes to assert an attack detection output responsive to sensing a logic state on the second node that is unexpected relative to a logic state on the first node.Type: ApplicationFiled: September 28, 2022Publication date: March 28, 2024Applicant: NVIDIA Corp.Inventors: Kedar Rajpathak, Tezaswi Raja
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Patent number: 11923853Abstract: A ring oscillator circuit with a frequency that is sensitive to the timing of a clock-to-Q (clk2Q) propagation delay of one or more flip-flops utilized in the ring oscillator. The clock2Q is the delay between the clock signal arriving at the clock pin on the flop and the Q output reflecting the state of the input data signal to the flop. Clk2q delay measurements are made based on measurement of the ring oscillator frequency, leading to more accurate estimates of clk2Q for different types of flip-flops and flip-flop combinations, which may in turn enable improvements in circuit layouts, performance, and area.Type: GrantFiled: February 25, 2022Date of Patent: March 5, 2024Assignee: NVIDIA CORP.Inventors: Tezaswi Raja, Prashant Singh
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Patent number: 11777483Abstract: In various embodiments, a comparison circuit compares voltages within an integrated circuit. The comparison circuit includes a comparison capacitor, an inverter, and multiple switches. A first terminal of the comparison capacitor is coupled to both a first terminal of a first switch and a first terminal of a second switch. A second terminal of the comparison capacitor is coupled to both a first terminal of a third switch and an input of the inverter. An output of the inverter is coupled to both a second terminal of the third switch and a first terminal of a fourth switch. A second terminal of the fourth switch is coupled to a first terminal of a fifth switch and a first output of the comparison circuit. At least a portion of the switches are turned on during a comparison model and are turned off during a reset mode.Type: GrantFiled: March 18, 2022Date of Patent: October 3, 2023Assignee: NVIDIA CorporationInventors: Nishit Harshad Shah, Ting Ku, Krishnamraju Kurra, Gunaseelan Ponnuvel, Tezaswi Raja, Suhas Satheesh
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Publication number: 20230299760Abstract: In various embodiments, a comparison circuit compares voltages within an integrated circuit. The comparison circuit includes a comparison capacitor, an inverter, and multiple switches. A first terminal of the comparison capacitor is coupled to both a first terminal of a first switch and a first terminal of a second switch. A second terminal of the comparison capacitor is coupled to both a first terminal of a third switch and an input of the inverter. An output of the inverter is coupled to both a second terminal of the third switch and a first terminal of a fourth switch. A second terminal of the fourth switch is coupled to a first terminal of a fifth switch and a first output of the comparison circuit. At least a portion of the switches are turned on during a comparison model and are turned off during a reset mode.Type: ApplicationFiled: March 18, 2022Publication date: September 21, 2023Inventors: Nishit Harshad SHAH, Ting KU, Krishnamraju KURRA, Gunaseelan PONNUVEL, Tezaswi RAJA, Suhas SATHEESH
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Publication number: 20230289507Abstract: During a testing of a circuit design, an adaptive clock model and a voltage noise model are utilized within the computer implemented method of the testing environment in order to determine the dynamic effects of voltage variation and adaptive clock on the timing of the circuit design. The computer implemented method uses a hybrid stage that incorporates both a graph-based approach and a path-based approach may also be incorporated into the testing environment in order to maximize a performance of the testing of the circuit design.Type: ApplicationFiled: March 11, 2022Publication date: September 14, 2023Inventors: Chunhui Li, Sreedhar Pratty, Tezaswi Raja, Wen Yueh, Vinayak Bhargav Srinath
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Publication number: 20230275572Abstract: A ring oscillator circuit with a frequency that is sensitive to the timing of a clock-to-Q (clk2Q) propagation delay of one or more flip-flops utilized in the ring oscillator. The clock2Q is the delay between the clock signal arriving at the clock pin on the flop and the Q output reflecting the state of the input data signal to the flop. Clk2q delay measurements are made based on measurement of the ring oscillator frequency, leading to more accurate estimates of clk2Q for different types of flip-flops and flip-flop combinations, which may in turn enable improvements in circuit layouts, performance, and area.Type: ApplicationFiled: February 25, 2022Publication date: August 31, 2023Applicant: NVIDIA Corp.Inventors: Tezaswi Raja, Prashant Singh
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Publication number: 20230146920Abstract: Introduced herein is a technique that reliably measures on-die noise of logic in a chip. The introduced technique places a noise measurement system in partitions of the chip that are expected to cause the most noise. The introduced technique utilizes a continuous free-running clock that feeds functional frequency to the noise measurement circuit throughout the noise measurement scan test. This allows the noise measurement circuit to measure the voltage noise of the logic during a shift phase, which was not possible in the conventional noise measurement method. Also, by being able to measure the voltage noise during a shift phase and hence in both phases of the scan test, the introduced technique can perform a more comprehensive noise measurement not only during ATE testing but as part of IST in the field.Type: ApplicationFiled: November 2, 2022Publication date: May 11, 2023Inventors: Bonita Bhaskaran, Nithin Valentine, Shantanu Sarangi, Mahmut Yilmaz, Suhas Satheesh, Charlie Hwang, Tezaswi Raja, Kevin Zhou, Sailendra Chadalavada, Kevin Ye, Seyed Nima Mozaffari Mojaveri, Kerwin Fu
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Patent number: 11619661Abstract: In various embodiments, a current measurement circuit measures an input current within an integrated circuit. The current measurement circuit includes an integration capacitor, an operational amplifier, a comparison capacitor, an inverter, and multiple switches. The current measurement circuit is coupled to a clocking circuit that, during operation, generates a two-phase clock having a frequency that is proportional to the input current. At least a portion of the switches are turned on during a first phase of the two-phase clock and are turned off during a second phase of the two-phase clock.Type: GrantFiled: March 18, 2022Date of Patent: April 4, 2023Assignee: NVIDIA CorporationInventors: Nishit Harshad Shah, Ting Ku, Krishnamraju Kurra, Gunaseelan Ponnuvel, Tezaswi Raja, Suhas Satheesh
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Patent number: 11487341Abstract: Systems and techniques for improving the performance of circuits while adapting to dynamic voltage drops caused by the execution of noisy instructions (e.g. high power consuming instructions) are provided. The performance is improved by slowing down the frequency of operation selectively for types of noisy instructions. An example technique controls a clock by detecting an instruction of a predetermined noisy type that is predicted to have a predefined noise characteristic (e.g. a high level of noise generated on the voltage rails of a circuit due to greater amount of current drawn by the instruction), and, responsive to the detecting, deceasing a frequency of the clock. The detecting occurs before execution of the instruction. The changing of the frequency in accordance with instruction type enables the circuits to be operated at high frequencies even if some of the workloads include instructions for which the frequency of operation is slowed down.Type: GrantFiled: July 2, 2019Date of Patent: November 1, 2022Assignee: NVIDIA CORPORATIONInventors: Aniket Naik, Tezaswi Raja, Kevin Wilder, Rajeshwaran Selvanesan, Divya Ramakrishnan, Daniel Rodriguez, Benjamin Faulkner, Raj Jayakar, Fei (Walter) Li
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Patent number: 11327553Abstract: Digital low-dropout micro voltage regulator configured to accept an external voltage and produce a regulated voltage. All active devices of the voltage regulator are digital devices. All signals of the voltage regulator, except the first voltage and the regulated voltage, may be characterized as digital signals. Some active devices of the voltage regulator may be physically separated from other active devices of the voltage regulator by active devices of non-voltage regulator circuitry.Type: GrantFiled: May 20, 2021Date of Patent: May 10, 2022Assignee: NVIDIA CORPORATIONInventors: Siddharth Saxena, Tezaswi Raja, Fei Li, Wen Yueh
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Patent number: 11320892Abstract: Digital low-dropout micro voltage regulator configured to accept an external voltage and produce a regulated voltage. All active devices of the voltage regulator are digital devices. All signals of the voltage regulator, except the first voltage and the regulated voltage, may be characterized as digital signals. Some active devices of the voltage regulator may be physically separated from other active devices of the voltage regulator by active devices of non-voltage regulator circuitry.Type: GrantFiled: December 8, 2020Date of Patent: May 3, 2022Assignee: NVIDIA CORPORATIONInventors: Siddharth Saxena, Tezaswi Raja, Fei Li, Wen Yueh
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Patent number: 11276648Abstract: An on-chip electromagnetic (EM) pulse protection circuit detects EM pulse attacks, generates an alarm, and performs a defensive action to protect the integrated circuit. The EM pulse protection circuit can be used with various integrated circuits or manufactured chips in which, for example, there is a desire to keep information secure, maintain the security of the chip, secure boot processes, and/or protect private keys.Type: GrantFiled: July 31, 2018Date of Patent: March 15, 2022Assignee: Nvidia CorporationInventors: Chinmay Apte, Brian Smith, Tezaswi Raja, Roman Surgutchik
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Patent number: 11131711Abstract: In-chip decoupling capacitor circuits refer to decoupling capacitors (DCAPs) that are placed on a chip. These DCAPs are generally used to manage power supply noise for the chip, and can be utilized individually or as a distributed system. In some cases, DCAPs may make up a significant portion of the chip. Unfortunately, defects in DCAPs will degrade over time, will encroach into active logic, and will further cause automatic test pattern generation (ATPG) failure. To date, there has been a lack of structural test coverage for DCAP circuits, which reduces test coverage of the chip as a whole. To this end, defects on the chip as they relate to DCAPs (i.e. shorts in the DCAP) may not be detected. The present disclosure provides a structural test system and method for DCAPs and other passive logic components located on-chip.Type: GrantFiled: July 22, 2020Date of Patent: September 28, 2021Assignee: NVIDIA CORPORATIONInventors: Krishnamraju Kurra, Gunaseelan Ponnuvel, Divyesh Shah, Abhishek Akkur, Kartik Joshi, Tezaswi Raja, Andy Chamas
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Publication number: 20210294410Abstract: A circuit includes a supply power detector in a first power domain and a ratioed inverter in the first power domain or a second, different power domain. The supply power detector includes an output coupled to an input of the ratioed inverter, and an output of the ratioed inverter provides a power sequencing signal for the second power domain.Type: ApplicationFiled: May 26, 2021Publication date: September 23, 2021Applicant: NVIDIA Corp.Inventors: Kedar Rajpathak, Tezaswi Raja
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Publication number: 20210271312Abstract: Digital low-dropout micro voltage regulator configured to accept an external voltage and produce a regulated voltage. All active devices of the voltage regulator are digital devices. All signals of the voltage regulator, except the first voltage and the regulated voltage, may be characterized as digital signals. Some active devices of the voltage regulator may be physically separated from other active devices of the voltage regulator by active devices of non-voltage regulator circuitry.Type: ApplicationFiled: May 20, 2021Publication date: September 2, 2021Inventors: Siddharth Saxena, Tezaswi Raja, Fei Li, Wen Yueh
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Patent number: 11048321Abstract: Digital low-dropout micro voltage regulator configured to accept an external voltage and produce a regulated voltage. All active devices of the voltage regulator are digital devices. All signals of the voltage regulator, except the first voltage and the regulated voltage, may be characterized as digital signals. Some active devices of the voltage regulator may be physically separated from other active devices of the voltage regulator by active devices of non-voltage regulator circuitry.Type: GrantFiled: June 1, 2018Date of Patent: June 29, 2021Assignee: NVIDIA CORPORATIONInventors: Siddharth Saxena, Tezaswi Raja, Fei Li, Wen Yueh
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Patent number: 10990732Abstract: Introduced herein is an improved technique of recovering system frequency margin via distributed CPMs. The introduced technique creates and distributes multiple sets of always sensitized critical path replicas across a chip and monitors them for timing failure. The introduced technique takes feedback from these critical path replicas and dynamically boosts the clock frequency of the chip to remove the margin. The introduced technique provides more accurate and more comprehensive coverage of a chip performance.Type: GrantFiled: January 30, 2020Date of Patent: April 27, 2021Assignee: Nvidia CorporationInventors: Tezaswi Raja, Siddharth Saxena, Ben Faulkner, Sachin Idgunji, Vinayak Bhargav Srinath, Wen Yueh, Chad Plummer, Kartik Joshi
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Publication number: 20210089112Abstract: Digital low-dropout micro voltage regulator configured to accept an external voltage and produce a regulated voltage. All active devices of the voltage regulator are digital devices. All signals of the voltage regulator, except the first voltage and the regulated voltage, may be characterized as digital signals. Some active devices of the voltage regulator may be physically separated from other active devices of the voltage regulator by active devices of non-voltage regulator circuitry.Type: ApplicationFiled: December 8, 2020Publication date: March 25, 2021Inventors: Siddharth Saxena, Tezaswi Raja, Fei Li, Wen Yueh
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Patent number: 10929591Abstract: Various embodiments of the disclosure disclosed herein provide techniques for pre-silicon testing of a design for an integrated circuit. A pre-silicon testing system identifies one or more critical paths included in the integrated circuit. The pre-silicon testing system performs a based noise simulation to generate one or more voltage waveforms at each gate associated with the one or more critical paths. The pre-silicon testing system applies the one or more voltage waveforms to one or more netlists corresponding to the one or more critical paths to generate one or more modified netlists. The pre-silicon testing system performs a timing analysis on the one or more modified netlists to determine a set of slack times that correspond to a set of voltages applied to the integrated circuit. The pre-silicon testing system determines a first critical path that has a lowest slack time relative to all other critical paths.Type: GrantFiled: July 18, 2019Date of Patent: February 23, 2021Assignee: NVIDIA CorporationInventors: Tezaswi Raja, Prashant Singh, Vinayak Bhargav Srinath, Wen Yueh
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Patent number: RE49711Abstract: Digital low-dropout micro voltage regulator configured to accept an external voltage and produce a regulated voltage. All active devices of the voltage regulator are digital devices. All signals of the voltage regulator, except the first voltage and the regulated voltage, may be characterized as digital signals. Some active devices of the voltage regulator may be physically separated from other active devices of the voltage regulator by active devices of non-voltage regulator circuitry.Type: GrantFiled: February 4, 2022Date of Patent: October 24, 2023Assignee: NVIDIA CORPORATIONInventors: Siddharth Saxena, Tezaswi Raja, Fei Li, Wen Yueh