Abstract: An apparatus for quadrature tuner error correction includes an offset correction circuit adapted to receive a digital in-phase signal and a digital quadrature signal from a quadrature tuner. The offset correction circuit has an in-phase circuit comprising a summer adapted to receive the digital in-phase signal, subtract an in-phase offset estimate therefrom, and generate an offset corrected in-phase signal, and a feedback loop adapted to integrate the offset corrected in-phase signal, multiply the integrated offset corrected in-phase signal by a first adjustable constant, and generate the in-phase offset estimate.

Abstract: A digital tuner 70 for maximizing tuning range for a particular intermediate frequency includes an analog to digital converter (78) operating at an input clock frequency to sample an analog input signal (76) and output a multi-bit digital word for each sample, a demultiplexer (82) in communication with the analog to digital converter (78) and a plurality of mixers (84) to convert serial samples from the analog to digital converter (78) to parallel samples for input to the mixers (84) functioning as quadrature multipliers, local oscillators (86) in communication with corresponding ones of the mixers (84), and a parallel cascaded integrator comb filter (72, 74) in communication with the mixers (84) for filtering and decimating the parallel samples, where the mixers (84), the local oscillators (86), and the filter (72, 74) operate at a frequency having adjacent harmonics substantially centered about the intermediate frequency.

Abstract: A method for generating a trigonometric function is provided that includes an input angle being received and automatically separated into a first component angle and a second component angle. A sine value for the input angle is automatically determined based upon the first and second component angles. A cosine value for the input angle is automatically determined based upon the first and second component angles. The trigonometric function is automatically generated based upon the sine and cosine values for the input angle.

Abstract: A parallel asynchronous sample rate reducer (26) for converting a synchronous parallel digital input signal (INP_DAT) into a parallel digital output signal (OUT_DAT) having an average aggregate sample rate that is asynchronous with respect to the input sample clock rate. The sample rate reducer (26) includes a parallel phase accumulator (36) for determining the output sample number values and the fractional phase values corresponding to each output sample number combined in an output value (PHS_ACC). Control logic (34) receives the phase accumulator output value PHS_ACC and generates an interpolator value (CTL_INT) for controlling interpolation of the input data to interpolate the data to the predetermined output sample number and the corresponding fractional phase values. The control logic (34) also generates control a build value (CTL_BLD) to enable alignment of the interpolated data signals.

Abstract: Apparatus for phase/frequency digital modulation includes a digital circuit receiving and processing a digital modulation input signal to generate a digital modulation control signal, a digital-to-analog converter coupled to the digital circuit converts the digital modulation control signal into an analog modulation control signal, and an RF/analog circuit is coupled to the digital-to-analog converter. The RF/analog circuit includes a voltage controlled oscillator to generate a modulated output signal in response to the analog modulation control signal, and a quadrature tuner coupled to the voltage controlled oscillator generates an in-phase tuner output and a quadrature tuner output in response to the modulated output signal. An analog-to-digital converter is coupled to the quadrature tuner and converts the in-phase tuner output and the quadrature tuner output to digital in-phase and quadrature tuner outputs.

Abstract: A configurable interface module particularly suited for processing of digital and analog information includes at least one field programmable gate array (44, 46, 48) mounted on a mezzanine board (30) to provide functional flexibility and not requiring an additional slot in a computer chassis. In a preferred embodiment, the module is utilized to process weather information and performs the functions of demodulation, bit and frame synchronization, and FIFO buffer control. The gate arrays may be reprogrammed to implement either AM demodulation or BPSK demodulation or adapted to process other types of information, such as telemetry information.

Abstract: A configurable interface module particularly suited for processing of digital and analog information includes at least one field programmable gate array (44, 46, 48) mounted on a mezzanine board (30) to provide functional flexibility and not requiring an additional slot in a computer chassis. In a preferred embodiment, the module is utilized to process weather information and performs the functions of demodulation, bit and frame synchronization, and FIFO buffer control. The gate arrays may be reprogrammed to implement either AM demodulation or BPSK demodulation or adapted to process other types of information, such as telemetry information.

Abstract: A high speed digital filter for use in digital interpolation and decimation provides a parallel processing implementation for integrator stages of a cascaded integrator-comb (CIC) filter. The parallel structure of the present invention is easily cascadeable since it allows subsequent integrator stages access to intermediate samples generated by preceding integrator stages. The parallel integrator structure may be implemented directly or may be reduced in complexity by removing redundant logic for use in decimator output sections or interpolator input sections. The parallel implementation of a CIC filter allows much higher sample rate filtering to be implemented with fewer standard CMOS logic devices than currently recognized implementations.

Abstract: A high speed parallel frame synchronizer provides high speed frame synchronization functions utilizing parallel processing techniques implemented with commercially available components. Serial input data is demultiplexed to an N bit wide word at a rate of 1/N of the input clock frequency. A total of N parallel correlators are used to detect the frame synchronization pattern. Outputs of the correlators are arbitrated using a priority encoder which provides synchronization information to the frame synchronizer. One embodiment of this invention utilizes 4N correlators to simultaneously provide for synchronization of true/inverted and forward/reverse data generated by real-time or playback data sources.

Abstract: A general purpose continuous phase modulator is shown which greatly reduces the amount of memory and associated hardware complexity traditionally found in continuous phase modulators. The continuous phase modulator includes a phase accumulator which calculates the phase state in an on-line real time fashion. As a result, a continuous phase modulator is provided which is adaptable to any transmitter or transceiver product requiring power and bandwidth efficiency such as those found in satellite communications equipment.

Abstract: A sample and hold circuit which achieves both a fast acquisition time and a low droop rate is disclosed. FET or analog switches form a sample switch. When this circuit is in a hold mode the sample switch is biased so that no voltage appears across the switch. However, only one switch or a plurality of switches in parallel connect between a driving buffer and hold capacitor so that a fast acquisition time is achieved when this circuit is in a sample mode.

Abstract: Generating a digital signal from the output of a numerically controlled oscillator and delaying certain transitions of the digital to produce an output digital signal having a generally 50% duty cycle and a frequency determined by a frequency select input to the numerically controlled oscillator.

Abstract: An improved evaporative cooler contains a first pump for supplying cooling liquid to the evaporative pads and a second pump for draining liquid in the sump pan through a drain/overflow pipe. Both pumps are coupled to an electronic control mechanism which activates the first pump for a first predetermined period of time within each successive second predetermined period of time (e.g. the first 2.5 minutes of every successive 10 minute period). The control mechanism causes the second pump to drain the sump pan through the drain/overflow pipe for a third predetermined period of time following the first occurence of the first predetermined period of time (e.g. for 5.0 minutes after the first 2.5 minute wetting cycle). This draining process occurs only once each time the evaporative cooler is turned on. The drain/overflow pipe has an upper end coupled to the outlet of the second pump and also has an aperture in the wall thereof through which excess liquid in the sump pump will flow and be discharged.

Abstract: Apparatus and method for generating an output signal as a function of an input, or reference signal. The apparatus consists of a numerically controlled oscillator having an output signal whose output frequency is determined by the input of a pair of frequency select inputs to the NCO. A control unit operates a multiplexer which allows one of the pair of frequency select inputs to be transmitted to the NCO. The increase in the number of variables provides an increase in the number of different step frequencies the FMD may be operated at.

Abstract: A synchronous carry frequency divider having a series of counters wherein each pair of counters is separated by a flip-flop and wherein the last counter in the series is followed by a terminal flip-flop. The counters and the flip-flops are synchronously clocked so that the divisor ratio is increased by the number of flip-flops employed. When the terminal flip-flop is toggled by the last counter a terminal count signal and a preset enable signal are simultaneously achieved without the delays associated with terminal count decode networks.

Abstract: A radio frequency numerically controlled oscillator comprising N one bit adders each providing sum and carry outputs to one of N two bit registers. Sum, carry and frequency selection inputs are combined by each adder to form sum and carry outputs. These results are held by the associated register when triggered by a clock input. A fast parallel adder/latch is employed which has two stages connected serially to generate sums on opposite phases of a two phase clock.

Abstract: Generating apparatus providing a preferred pulse envelope which is compared to the envelope of output pulses from a nonlinear power amplifier, the error between the two being used, along with a stored predistorted pulse, to generate an updated predistorted pulse that is utilized to modulate the input signal to the nonlinear amplifier to produce a pulse at the output thereof having the preferred envelope and to update the stored predistorted pulse.

Abstract: A scan rate switch is interfaced to a microprocessor which controls a digitally programmed frequency synthesizer. The scan rate switch includes a plurality of different increment or decrement (frequency steps) positions with the apparatus changing the frequency at a fixed rate of five steps per second for as long as the switch is in any of the positions.

Abstract: A font of characters including a first set defined by dots and a second set outlined by dots and used as a cursor, and a plurality of characters each forming a line segment and combinable in differing quantities and types to form a bar graph presentation, measured characteristics being displayed by digital and bar graph presentations simultaneously and the bar graphs being variable in either or both directions from a reference point such as zero.