Abstract: A static latch circuit is used to suppress crosstalk glitch in a synchronous digital integrated circuit. A static latch is inserted into a selected victim net, and the net is examined if crosstalk glitch induced in the selected victim net is sufficiently suppressed. If not, then the selected victim net is examined to check whether the crosstalk glitch is primarily due to propagated noise from an earlier stage or due to noise injected in the selected victim net. If the crosstalk glitch is propagated from an earlier stage, then a second static latch is inserted before the state in which the first static latch is inserted. Alternatively, another static latch may be inserted in the selected victim net. Cell libraries including a variety of static latch circuit architectures can be designed.

Abstract: A maximum a posteriori (MAP) processor employs a block processing technique for the MAP algorithm to provide a parallel architecture that allows for multiple word memory read/write processing and voltage scaling of a given circuit implementation. The block processing technique forms a merged trellis with states having modified branch inputs to provide the parallel structure. When block processing occurs, the trellis may be modified to show transitions from the oldest state at time k?N to the present state at time k. For the merged trellis, the number of states remains the same, but each state receives 2N input transitions instead of the two input transitions. Branch metrics associated with the transitions in the merged trellis are cumulative, and are employed for the update process of forward and backward probabilities by the MAP algorithm.

Abstract: A wireless communication network includes position-based capacity reservation of base stations. Using, for example, the Global Positioning System (GPS), a mobile unit may periodically determine its position and communicate its position to base stations as the mobile unit moves through the network. In addition, the capacity needs of the mobile unit's connection may be communicated expressly by the unit or deduced from the connection itself. A network management system receives the position and capacity information of the mobile unit, and then estimates a route of the mobile unit through the network. Such route may be determined either 1) explicitly, given information transmitted by the mobile unit or 2) implicitly, by tracking the direction of movement of the mobile unit through the network. Consequently, the network management system may determine the availability of capacity of base stations along the estimated route through the network.

Abstract: A maximum a posteriori (MAP) processor employs a block processing technique for the MAP algorithm to provide a parallel architecture that allows for multiple word memory read/write processing and voltage scaling of a given circuit implementation. The block processing technique forms a merged trellis with states having modified branch inputs to provide the parallel structure. When block processing occurs, the trellis may be modified to show transitions from the oldest state at time k−N to the present state at time k. For the merged trellis, the number of states remains the same, but each state receives 2N input transitions instead of the two input transitions. Branch metrics associated with the transitions in the merged trellis are cumulative, and are employed for the update process of forward and backward probabilities by the MAP algorithm.

Abstract: A circuit for extracting a common mode data signal applied to a plurality of component signals. The circuit including a current driver, resistance, and a common mode extraction unit connected in series. The extraction unit has an impedance substantially proportional to the average voltage of the applied input signals and may be formed of a series of matched transistors connected in parallel. In a single-path configuration, when pairs of differential signals are applied, the voltage drop across the extraction unit is proportional to the overall common mode signal level carried by the differential signal components. In a multiple path configuration, two or more extraction units may be connected to a common current driver and configured in a differential amplifier configuration.

Abstract: A tuning signal is injected into an LC tank circuit oscillator, e.g., through an impedance (either reactive, inductive, capacitive and/or resistive) to tune the phase and/or frequency of the LC tank circuit oscillator. A negative resistance is included in parallel with the LC tank circuit oscillator to compensate for losses in the LC tank circuit, and a bias signal is provided to power the operation of the LC tank circuit. Multiple LC tank circuit oscillators may be used to provide stable multiplied or divided frequencies. In another embodiment, the nominal frequency of the LC tank circuit oscillator may be adjusted using a varactor or other voltage-controlled element in the LC tank circuit oscillator under the control of, e.g., the output of a separate PLL loop including another LC tank circuit oscillator. In one application, the injection tuned LC tank circuit forms a clock recovery cell using a clock signal embedded in a NRZ (Non Return to Zero) pseudo-random data stream.

Abstract: A method and system for tuning a tunable bandpass filter includes a bandpass filter having a passband which is dependant on the value of a tuning signal. A data signal having a dominant frequency component is applied to the filter and the power of the signal passed by the filter is determined. The tuning signal is adjusted until the passed power is maximized, indicating that the filter is tuned to the dominant frequency. The tuning signal can then be applied to other tunable circuits, including an oscillator having an output used as a clock signal to extract data from the data signal applied to the filter.

Abstract: A system and method for transferring digital data using differential and common mode data signaling is disclosed. A first digital data signal is differentially transmitted using two differential signal components sent over a two-wire interface and switched between several different discrete signal levels. A common mode signal is carried across the differential pair and used to transmit a second digital data signal. The data output stage uses a common mode injection circuit to inject a common mode voltage or current equally onto both components of the differential interface. The data receiver has a common mode extraction circuit connected to the differential interface which extracts the injected common mode signal. Common mode data transmission can be in the same or opposite direction as the differential data transmission. Common mode signals may be injected in several layers and across two or more differential interfaces to increase the data content per interface line and to improve accuracy.

Abstract: A passive resistive element is provided in series with a digital variable impedance to produce a highly linear output impedance for a transmission path over a wide range of operating conditions.

Abstract: A resistor circuit having its impedance controlled by a DC voltage is provided. The resistor circuit includes a first resistor with an expected impedance. The circuit also includes a second resistor connected in series with a DC voltage controlled transistor. The first resistor is placed in parallel with the series connection of the second resistor and the transistor. Adjustments to the impedance of the circuit occur by adding or removing the impedances of the second resistor and transistor by varying the DC voltage applied to the transistor. In doing so, the impedance of the resistor circuit will be controlled to match a desired impedance regardless of the variations caused by the manufacturing process, operating temperature or operating power supply voltage.

Abstract: A hot clock adiabatic gate, using CMOS technology, incorporates an ancillary transistor. The gate is energized by multiple clock signals of different phases to reduce power consumption. The output logic voltage of the gate can reach full-rail voltage by allowing the CMOS technology to discharge via the ancillary transistor. The hot clock adiabatic gate and associated ancillary transistor may be incorporated into various logic circuits, such as an inverter, a memory cell, a NAND gate, and a NOR gate. In one configuration, a CMOS inverter is controlled by four clock signals having four discrete phases. The CMOS inverter optimally includes a CMOS gate transistor pair wherein the semiconductor channels of two ancillary transistors are in series with the semiconductor channels of the CMOS gate transistor pair.

Abstract: The output frequency of a simple low-power-dissipation oscillator circuit designed to drive PPS CMOS circuits is controlled by a closed-loop system. In response to deviations of the output frequency from a prescribed value, the system generates correction signals that are applied to an array of capacitors. In that way, capacitance is electrically added to or subtracted from a series-resonant path of the oscillator circuit, thereby to automatically establish and maintain the output frequency of the circuit at or near its prescribed value.

Abstract: A relatively simple low-power-dissipation oscillator circuit comprises an inductor in series with a capacitor. Self-timing circuitry connected to an output node point between the inductor and the capacitor compensates for resistive losses in the circuit and thereby insures generation of a constant-amplitude output sine wave suitable for driving PPS CMOS circuitry. The oscillator circuit also includes starting and stopping circuitry connected to the inductor. To conserve power during so-called data inactive periods, the oscillator circuit can be abruptly stopped in a manner that preserves stored states in the CMOS circuitry and provides an output voltage suitable for powering conventional (non-PPS) CMOS circuitry while establishing a reliable basis for subsequently reinitiating oscillations.

Abstract: CMOS integrated circuit buffers typically use a dual-diode electrostatic discharge (ESD) protection technique. However, in some cases that technique inadvertently causes one of the diodes to conduct when a desired signal voltage is present on the bondpad, thereby clipping the desired signal. This occurs, for example, when an output buffer on an unpowered device is connected to an active bus, or when the input buffer of a 3 volt device receives a 5 volt signal. The present invention solves this problem by using a bipolar (e.g., pnp) protection transistor connected between the bondpad and a power supply bus (e.g., V.sub.SS). The base of the transistor is connected to the bondpad through a resistor that provides a time delay due to the R-C time constant that includes distributed capacitance. The time delay allows for a high conduction period, during which an ESD event is conducted through the bipolar transistor, thereby protecting the input or output buffer.

Abstract: In low-power-dissipation CMOS circuitry, conventional CMOS inverters are powered by a repetitively ramped power supply. Clock signals are needed in the circuitry for controlling data flow therein. To ensure optimal low-power operation of the circuitry, clock signals are derived directly from the ramped power supply waveform itself. Additionally, a technique similar to that employed in the clock-signal-generating arrangement is utilized to propagate digital data signals between chips in a low-power way.

Abstract: High-frequency, low-power CMOS oscillators having electrically-tunable tank circuits are disclosed. Electrically-tunable inductors assure highly efficient oscillator operation and can be adjusted after manufacture to assure high yields of high-precision oscillator circuits.

Abstract: An advantageous hybrid data processing system includes both conventional CMOS circuitry and low-power-dissipation pulsed-power-supply (PPS) CMOS circuitry. To enable the different types of circuitry in the system to communicate with each other, data signal representations that are in a PPS format must be converted to corresponding conventional CMOS-formatted data signals before being processed by the CMOS circuitry. Similarly, conventional CMOS data signals must be converted to corresponding PPS-formatted representations before the signals can be processed by the PPS circuitry.

Abstract: A CMOS coupled-tank oscillator for VLSI circuit applications is disclosed. The coupled-tank oscillator has two inverters coupled, input-to-output, by inductances that may be simply wires, and a capacitance acting in parallel with each inverter that may be, simply, the invert's gate capacitance. The invention permits 0.9-micron CMOS oscillators to produce high-frequency signals.

Abstract: A multi-chip module is composed of two or more integrated-circuit chips located on a substrate such as a dielectrically coated silicon substrate. The chips are interconnected by means of transmission wiring lines. At least some of the chips contain one or more input buffer circuits, each composed of two branches ("legs"). Each such branch contains, in one embodiment, an n-channel MOS transistor connected in series with a pair of series-connected p-channel MOS transistors--whereby, in each such branch, one of the p-channel MOS transistors is located between (intermediate) the other of the p-channel MOS transistors and the n-channel MOS transistor of that same branch. On the other hand, in each buffer circuit, the intermediate p-channel MOS transistors of both branches are cross-coupled.

Abstract: A conventional CMOS inverter circuit is operated in a low-power-dissipation mode by being connected to a pulsed power supply. The circuit is utilized as a basic building block to realize a variety of logic and memory functions.