Abstract: In non-volatile memory devices, a write typically consists of an alternating set of pulse and verify operations. At the end of a pulse, the device must be biased properly for an accurate verify, after which the device is re-biased for the next pulse. In some cases a non-volatile memory is programmed by an alternating set of pulses, but, for at least some pulses without any intervening verify operations. After a one pulse, but before biasing the memory for the next pulse without an intervening very, the source and bit line levels can be left to float.

Abstract: An electrical connector system includes a backplane connector having a housing, signal contacts held by the housing and shield plates held by the housing. The housing includes a front and a rear. The housing includes signal channels extending along mating axes thereof between the front and the rear. The signal channels receive corresponding signal contacts. The housing includes slots that receive the shield plates. The signal contacts extend along the mating axes and are arranged in pairs carrying differential signals. The shield plates are electrically conductive and extend generally parallel to the mating axes between corresponding pairs of signal contacts to entirely peripherally surround the pairs of signal contacts to provide electrical shielding for the pairs of signal contacts.

Abstract: In a programming operation that includes repeated bitscan, program, and verify steps, the bitscan steps may be hidden by performing bitscan in parallel with program preparation and program steps. The effect of a program step may be predicted from previous observation so that when a bitscan indicates that the memory cells are close to being programmed, a last programming step may be completed without subsequent verification or bitscan steps.

Abstract: A compact and versatile high speed sense amplifier suitable for use in non-volatile memory circuits is presented. The sense amp circuit uses one power supply level for the bit line driving path and a second supply level for a data latch of the sense amp. The latch's supply level is of a high level that used for driving the bit lines and can be provided by a charge pump. The sense amp need use only NMOS devices for its analog path. For balancing performance and current consumption, the sense amp also includes an additional latch to support a “hybrid lockout” sensing mode, where in a verify operation a read-lockout is used between different data states, but not between the low and high quick pass write (QPW) verifies.

Abstract: A compact and versatile high speed sense amplifier suitable for use in non-volatile memory circuits is presented. The sense amp circuit is connected to first and second supply levels, a first level used for setting a program inhibit level on bit lines and a second level used for pre-charging bit lines for sensing operation. Outside of a data latch, the sense amp can employ only NMOS transistors. The arrangement of the circuit also allows for the discharging the bit line at the same time as transfers the sensing result out to other latches.

Abstract: A compact and versatile high speed sense amplifier suitable for use in non-volatile memory circuits is presented. The sense amp includes a latch, which is connected to a data bus, and bit line selection circuitry by which it can selectively be connected to one or more bit lines. The sense amp also includes some intermediate circuitry having a first node connectable to a selected bit line through the bit line selection circuitry and a second node that is connectable to the latch circuit. The sense amp can include switches where the second node can be connected to either the value held in the latch or the inverse of the value held in the latch. The sense amp can also include a switch where an internal node of the sense amp can be connected directly to a voltage supply level.

Abstract: Non-hydrophobic beads and methods to reversibly bind, normalize, store and in situ deliver primers to reactions including PCR. Also provided are instructions for preparing the beads. In the presence of an appropriate binding buffer, a bead can be used to bind and desalt primers from a crude solution of DMT-off primers. In the presence of an appropriate binding buffer, a bead can be used to bind and purify primers from a crude solution of DMT-on primers. A bead may bind a picomolar amount of DMT-on primers from a solution containing a plurality of crude DMT-on primers. Upon detritylation and washing, the resulting DMT-off primer bound bead may be used in PCR. Primers are released from the bead upon cycling the temperature. Primer bound beads are coated or silanized with hydrophobic reagents which ensures a gradual release of primers during the thermal cycling of the PCR reaction. Coating or silanization in turn enhances primer stability and long term storage.

Abstract: In non-volatile memory devices, a write typically consists of an alternating set of pulse and verify operations. At the end of a pulse, the device must be biased properly for an accurate verify, after which the device is re-biased for the next pulse. The intervals between the pulse and verify phases are considered. For the interval after a pulse, but before establishing the verify conditions, the source, bit line, and, optionally, the well levels can be equalized and then regulated at a desired DC level. After a verify phase, but before applying the biasing the memory for the next pulse, the source and bit line levels can be equalized to a DC level.

Abstract: In non-volatile memory devices, a write typically consists of an alternating set of pulse and verify operations. At the end of a pulse, the device must be biased properly for an accurate verify, after which the device is re-biased for the next pulse. In some cases a non-volatile memory is programmed by an alternating set of pulses, but, for at least some pulses without any intervening verify operations. After a one pulse, but before biasing the memory for the next pulse without an intervening very, the source and bit line levels can be left to float.

Abstract: In non-volatile memory devices, a write typically consists of an alternating set of pulse and verify operations. At the end of a pulse, the device must be biased properly for an accurate verify, after which the device is re-biased for the next pulse. The intervals between the pulse and verify phases are considered. For the interval after a pulse, but before establishing the verify conditions, the source, bit line, and, optionally, the well levels can be equalized and then regulated at a desired DC level. After a verify phase, but before applying the biasing the memory for the next pulse, the source and bit line levels can be equalized to a DC level.

Abstract: A method and system for of single view image 3D face synthesis. The method comprises the steps of a) extracting feature points from the single view image; b) transforming the feature points into 3D space; c) calculating radial basis function (RBF) parameters in 3D space based on the transformed feature points and corresponding points from a 3D generic model; d) applying RBF deformation to the generic 3D model based on the RBF parameters to determine a model for the synthesized 3D face; and e) determining texture coordinates for the synthesized 3D face in 2D image space; wherein step b) comprises symmetrically aligning the feature points, and step e) comprises projecting the generic 3D model or the model for the synthesized 3D face into 2D image space and applying RBF deformation to the projected generic 3D model or the projected model for the synthesized 3D face.

Abstract: A header connector includes a housing extending along a longitudinal axis between mating and mounting ends. The housing has contact channels open between the mating and mounting ends, and the housing has air pockets provided between selected ones of the contact channels to control an impedance of socket contacts received in the contact channels. Socket contacts are loaded into the contact channels, with each socket contact including a contact body extending along a longitudinal axis between mating and mounting ends. The contact body has a box-shaped socket at the mating end that defines a reception area configured to receive a mating contact. The box-shaped socket is configured to engage four different sides of the mating contact.

Abstract: In sensing a page of nonvolatile memory cells with a corresponding group of sense modules in parallel, as each high current cell is identified, it is locked out from further sensing while others in the page continued to be sensed. The sense module involved in the locked out is then in a lockout mode and becomes inactive. A noise source from the sense module becomes significant when in the lockout mode. The noise is liable to interfere with the sensing of neighboring cells by coupling through its bit line to neighboring ones. The noise can also couple through the common source line of the page to affect the accuracy of ongoing sensing of the cells in the page. Improved sense modules and method isolate the noise from the lockout sense module from affecting the other sense modules still active in sensing memory cell in the page.

Abstract: An electrical contact is provided for an electrical connector that is mounted on a printed circuit. The electrical contact includes a mating segment having a mating interface configured to engage a mating contact of another connector. The electrical contact also includes a tail segment having a mounting interface configured to be mounted to the printed circuit. An intermediate segment extends between and interconnects the mating and tail segments. The intermediate segment includes a base wall extending a length from the tail segment to the mating segment. The intermediate segment further includes a side wall extending outwardly from the base wall along at least a portion of the length of the base wall. The side wall extends outwardly at a non-parallel angle relative to the base wall for affecting at least one of an impedance, an insertion loss, or a reflection of the electrical contact.

Abstract: A technique for efficient power amplification includes providing multiple baseband signals to an amplifier. The signals may be converted to RF and combined through one or more impedance inverters.

Abstract: Sensing circuits for sensing a conduction current of a memory cell among a group of non-volatile memory cells being sensed in parallel and providing the result thereof to a data bus are presented. A precharge circuit is coupled to a node for charging the node to an initial voltage. An intermediate circuit is also coupled to the node and connectable to the memory cell, whereby current from the precharge circuit can be supplied to the memory cell. The circuit also includes a comparator circuit to perform a determination the conduction current by a rate of discharge at the node; a data latch coupled to the comparator circuit to hold the result of said determination; and a transfer gate coupled to the data latch to supply a result latched therein to the data bus independently of the node. This arrangement improves sensing performance and can help to eliminate noise on the analog sensing path during sensing and reduce switching current.

Abstract: An RFID reader is configured to be worn on the arm of a user and includes a housing with a bottom surface for facing the arm of a user and a top surface facing away from the arm. A securement structure engages the arm of the user to secure the housing. An antenna is mounted within the housing and is angled with respect to the bottom surface of the housing for providing an RF field at an angle to the arm of a user to direct the RF field toward an item held by the arm. The antenna includes an indexing structure with multiple angular positions for orientation of the antenna. A key structure is positioned in the housing and configured for engaging the indexing structure at an angular position around the antenna to orient the antenna at a desired rotational orientation in the housing to tune the antenna. Grip structures are formed along the top surface of the housing for gripping an item held by a user that contains an RFID tag that is read by the RFID reader.

Abstract: A high speed electrical connector assembly is disclosed providing a first subassembly having connector assemblies attached to a daughtercard, and a second subassembly having connector assemblies attached to a backplane. A keying guide module is mounted to the daughtercard and a keying guide pin is mounted to the backplane. The alignment of the keying guide module and keying guide pin aligns the connector assemblies on the daughtercard and backplane.

Abstract: A header connector includes a housing extending along a longitudinal axis between mating and mounting ends. The housing has contact channels open between the mating and mounting ends, and the housing has air pockets provided between selected ones of the contact channels to control an impedance of socket contacts received in the contact channels. Socket contacts are loaded into the contact channels, with each socket contact including a contact body extending along a longitudinal axis between mating and mounting ends. The contact body has a box-shaped socket at the mating end that clergies a reception area configured to receive a mating contact. The box-shaped socket is configured to engage four different sides of the mating contact.

Abstract: In sensing a page of nonvolatile memory cells with a corresponding group of sense modules in parallel, as each high current cell is identified, it is locked out from further sensing while others in the page continued to be sensed. The sense module involved in the locked out is then in a lockout mode and becomes inactive. A noise source from the sense module becomes significant when in the lockout mode. The noise is liable to interfere with the sensing of neighboring cells by coupling through its bit line to neighboring ones. The noise can also couple through the common source line of the page to affect the accuracy of ongoing sensing of the cells in the page. Improved sense modules and method isolate the noise from the lockout sense module from affecting the other sense modules still active in sensing memory cell in the page.