Abstract: A radar return signal is analyzed by amplitude comparators so as to classify the radar return signal with respect to 2.sup.n -1 threshold levels to thus produce n parallel bits for each classification defining the instantaneous amplitude of the radar return signal. The bits in a given significant bit position (most significant, least significant, etc.) comprise a word which moves through the video storage device serially with respect to bits in the same significant bit position and in parallel with respect to bits in the word comprised of different significance bits. Input buffers in the form of n storage registers are provided, each storage register being associated with a particular bit significance. The bits are entered into their associated storage register at a rate dependent upon the desired radar range. The bits are optionally integrated on a bit-by-bit basis and then entered into a main memory having n circulating storage registers arranged in parallel.