Abstract: A configuration control circuit in an integrated circuit device, such as a programmable logic device, having a programmable memory for storing configuration bits and one or more shift registers which are loadable from the memory. The memory is an array of nonvolatile memory cells that can be user programmed with data corresponding to a desired device architecture. The shift registers are loaded with this data upon power up or a reset. The registers in combination with other circuit gates control the operation of the device such that a particular architecture is implemented. The various configurations can be tested without altering the contents of the memory by loading the shift register externally.

Abstract: The present invention is an EPLD device having an integrated read and programming row driver using CMOS technology. A shared node is coupled to activate output inverters which drive row word lines. During the read mode, another CMOS inverter, which is coupled to a read input line, controls the signal on the node for driving the output inverters. During the programming mode a plurality of programming transistors which are coupled in series to the shared node is activated by address signals to pull the shared node to a lower potential. The integrated read and programming row driver circuit combination reduces the physical size of the associated circuity used in the pitched constrained area.