Abstract: A controller and a method for interfacing between a host and storage medium. A storage medium interface includes CH0 circuitry for performing a CH0 process to access a buffer memory on behalf of the storage medium. A host interface includes CH1 circuitry for performing a CH1 process to access the buffer memory on behalf of the host. Access to the buffer memory is arbitrated in sequential tenures to each channel of the multi-channel bus within a maximum arbitration round trip time defined by the time taken by the storage medium to move a distance corresponding to N sectors in which N is greater than one. In the CH0 tenure, the CH0 process transfers data corresponding to N sectors of the storage medium in a multi-sector burst. The length of the tenure of the CH0 channel is pre-designated so that the multi-sector burst is completed within the CH0 tenure.

Abstract: A method and system for processing data by a storage controller with a buffer controller coupled to a buffer memory is provided. The method includes, evaluating incoming data block size; determining if the incoming data requires padding; and padding incoming data such that the incoming data can be processed by the buffer controller. The method also includes determining if any pads need to be removed from data that is read from the buffer memory; and removing pads from the data read from the buffer memory. The buffer controller can be set in a mode to receive any MOD size data and includes a first channel with a FIFO for receiving incoming data via a first interface. The buffer controller mode for receiving incoming data can be set by firmware.

Abstract: A storage controller includes a memory controller that interfaces with memory that stores data. A first receive logic interface provides an interface to a host. A second receive logic interface provides an interface to a storage device. A power save module has a power save mode in which at least a clock of the memory controller is turned off while a clock for operating the first receive logic interface and the second receive logic interface is kept on.

Abstract: A controller for interfacing a host and storage device is provided. The controller includes a channel that can receive data from the storage device in a first format and store the data in an intermediate buffer memory in a second format. The channel includes conversion logic that converts data from the first format to the second format and from the second format to the first format depending upon whether data is being read or written from the buffer memory. The conversion logic uses a shuttle register and shuttle counter for aligning data that is being transferred between the storage device and the buffer memory by appropriately concatenating data to meet the first and second format requirements. The first format is based on 10-bit symbols and the second format is based on 8-bits.

Abstract: A system includes a data holding module that at least one of stores and receives data based on a first clock signal of a first clock domain. A data output module receives the data from the data holding module and selectively outputs the data based on a load signal and a second clock signal of a second clock domain which is asynchronous to the first clock domain. A synchronization process module generates the load signal based on a state of the data output module.

Abstract: A calibration module for a data storage control system. The calibration system includes a programmable delay module configured to i) receive a data strobe signal, ii) receive a delay value, and iii) output a delayed data strobe signal to a buffer based on the delay value, wherein data is read from the buffer based on the delayed data strobe signal. The calibration module further includes a delay calculation module configured to calculate the delay value based on a comparison between the data strobe signal and the delayed data strobe signal.

Abstract: A buffer control system for a data storage device controller comprises a command module and a burst module. The command module receives first channel data from a first channel having a first data format and second channel data from a second channel having a second data format and converts the first channel data and the second channel data to respective data packets each having a third data format that is different than the first data format and the second data format. The burst module that selectively transmits the data packets having the third data format to a memory in a single write burst.

Abstract: A write validation system that includes a first address signature collector module that generates a first address signature that is indicative of a write address of data when the data is received at a memory control module. A second address signature collector module generates a second address signature that is indicative of the write address of the data when the data is transferred from the memory control module. An address signature validation module receives the first address signature from the first address signature collector module, receives the second address signature from the second address signature collector module, and compares the first address signature to the second address signature.

Abstract: A calibration system for a data storage device includes a memory and a memory control module. The memory buffers data between a host and the data storage device and generates a data strobe signal. The memory control module selectively adjusts a delay of the data strobe signal. Data is read from the memory based on the data strobe signal.

Abstract: A circuit for reading data from a buffer memory, which is Synchronous Dynamic Random access Memory (“SDRAM”), or Double Data Rate-Synchronous Dynamic Random Access Memory (“DDR”) comprises logic for managing programmable clock signal relationships such that data that is read from the DDR is centered within a DQS signal which is generated from the DDR and then appropriately delayed.

Abstract: A memory system includes Synchronous Dynamic Random Access Memory (SDRAM) A memory controller communicates with the memory, generates an SDRAM clock signal, that receives a bi-directional sampling clock signal (DQS) that is generated based on the SDRAM clock signal, and reads data from the memory based on the DQS.

Abstract: A method and system using a storage controller for transferring data between a storage device and a host system is provided. The storage controller includes, a power save module that is enabled in a power save mode after a receive logic in the storage controller has processed all frames and during the power save mode at least a clock is turned off to save power while a clock for operating the receive logic is kept on to process any unsolicited frames that may be received by the receive logic. The storage controller operates in a single frame mode during the power save mode to process any unsolicited frames. Setting a bit in a configuration register for a processor enables the power save mode. The power save mode is enabled after a memory controller is in a self-refresh mode.

Abstract: A memory system comprises a memory that includes at least one of Synchronous Dynamic Random Access Memory (SDRAM) and Double Data Rate SDRAM (DDR). A memory controller communicates with the memory, generates an SDRAM clock signal, and receives a bi-directional sampling clock signal (DQS). When the memory includes the DDR, the memory generates the DQS. When the memory includes the SDRAM, the DQS is based on the SDRAM clock signal.

Abstract: A storage controller includes a first memory that stores a plurality of data blocks that include first and second noncontiguous data segments. A queue module stores data lengths and data start addresses of the first and second data segments. A read assembly module communicates with the first memory and the queue module, receives a request to read the first and second data segments from a host, reads the plurality of data blocks from the first memory, extracts the first and second data segments from the read plurality of data blocks based on the data lengths and data start addresses after the plurality of data blocks is read from the first memory, and transfers the first and second data segments contiguously to the host.

Abstract: A system and circuit for reading and writing data to a buffer memory, which is Synchronous Dynamic Random access Memory (“SDRAM”), or Double Data Rate-Synchronous Dynamic Random Access Memory (“DDR”) is provided. The circuit includes logic for managing programmable clock signal relationships such that data arrives at an optimum time for writing. Data that is to be written at DDR is moved from a first buffer clock to a DDR write clock signal and to a DQS signal that is based on a SDRAM clock signal. Also, plural tap-cells may be used to delay clock signals such that data and clock signals are aligned. An emulated DQS signal in a DDR capture scheme is used for reading from a SDRAM.

Abstract: A method and system for processing data by a storage controller with a buffer controller coupled to a buffer memory is provided. The method includes, evaluating incoming data block size; determining if the incoming data requires padding; and padding incoming data such that the incoming data can be processed by the buffer controller. The method also includes determining if any pads need to be removed from data that is read from the buffer memory; and removing pads from the data read from the buffer memory. The buffer controller can be set in a mode to receive any MOD size data and includes a first channel with a FIFO for receiving incoming data via a first interface. The buffer controller mode for receiving incoming data can be set by firmware.

Abstract: The present invention is related to methods and systems for context switching within a disk controller, allowing controller processors to efficiently switch between multiple tasks. In a first mode, a first memory is used to temporarily store data being transferred between a disk storage device coupled to the disk controller and a bus coupled to the disk controller. The transfer is managed by a disk controller processor. A first context is stored in a second memory coupled to the disk controller processor. In a second mode, the first memory is used to store a second context for later use by the disk controller processor. At least a portion of the first context information stored in the second memory is swapped with at least a portion of the second context information stored in the first memory at least partly in response to a first event. The swapped portion is then swapped back to the second memory in response to a second event.

Abstract: The present invention is related to systems and methods for a disk controller memory. In one embodiment, a mass storage device is interfaced to a computer via an I/O bus using a mass storage device controller. The mass storage device controller includes a processor and a buffer memory configured to receive data from the mass storage device and the I/O bus. In addition, the controller includes a memory circuit coupled to the buffer memory and the processor. The memory circuit is configured to operate as a first-in-first-out memory during at least a first transfer of data between the memory circuit and the buffer memory. For example, the memory may be configured to operate as either as a random access memory or a FIFO during at least a first transfer of data between the memory circuit and the processor.

Abstract: An interbus interface module enables storage and transfer of commands, messages and data between parallel a dual system bus operating on a first protocol and a subrequestor bus operating on a second protocol. The interface module serves a first group of requestors, such as multiple processors and main memory, for handling data transfers to and from the subrequestor bus via said dual system buses while also handling data transfers to and from a second group of requestors connected to the subrequestor bus.

Abstract: A network of digital modules having store-through and non-store-through cache memories, is provided with intercommunication capability by means of two sets of system busses each of which are replicates of each other. The system busses provide a higher throughput by both being available to each of the digital modules so that a requesting digital module can alternately use a second system bus if the first system bus happens to be busy. Failure of one system bus will allocate transmission service to the second operating system bus thus providing redundancy. Alternatively, each of the system busses can be isolated for partitioning the digital modules into two different operating systems which are independent of each other.