Patents by Inventor Theodore G. Tessier
Theodore G. Tessier has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9627254Abstract: An exemplary method includes forming a vertical pillar overlying or laterally displaced from a bond pad overlying a semiconductor substrate, and applying a discrete solder sphere in combination with one of a solder paste or flux on a top surface of the pillar, wherein the one of the solder paste or flux is defined by at least one photoresist layer. The method may include applying a solder sphere and/or solder flux in different combinations on top surfaces of different first and second pillars.Type: GrantFiled: March 14, 2013Date of Patent: April 18, 2017Inventors: Guy F. Burgess, Anthony P. Curtis, Eugene A. Stout, Theodore G. Tessier, Lillian C. Thompson
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Patent number: 9070747Abstract: Structures and methods provide a dielectric bridge for use in electroplating. A method comprises: providing a semiconductor wafer with a plurality of die, wherein a first die is adjacent to a second die, and the first die and second die are separated by a dicing street area; forming a patterned dielectric layer overlying the semiconductor wafer, the dielectric layer including a dielectric bridge that crosses the dicing street area; forming a conductive layer (e.g., a metal seed layer) overlying the dielectric layer, wherein a portion of the conductive layer is overlying the dielectric bridge to provide a current pathway from the first die to the second die; and electroplating targeted areas of the conductive layer by providing current to the second die using the current pathway. Other such bridges formed from the dielectric layer provide current pathways to other die on the wafer.Type: GrantFiled: September 27, 2013Date of Patent: June 30, 2015Assignee: Flipchip International LLCInventors: Eugene A. Stout, Douglas M. Scott, Anthony P. Curtis, Theodore G. Tessier, Guy F. Burgess
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Publication number: 20150001684Abstract: Structures and methods provide a dielectric bridge for use in electroplating. A method comprises: providing a semiconductor wafer with a plurality of die, wherein a first die is adjacent to a second die, and the first die and second die are separated by a dicing street area; forming a patterned dielectric layer overlying the semiconductor wafer, the dielectric layer including a dielectric bridge that crosses the dicing street area; forming a conductive layer (e.g., a metal seed layer) overlying the dielectric layer, wherein a portion of the conductive layer is overlying the dielectric bridge to provide a current pathway from the first die to the second die; and electroplating targeted areas of the conductive layer by providing current to the second die using the current pathway. Other such bridges formed from the dielectric layer provide current pathways to other die on the wafer.Type: ApplicationFiled: September 27, 2013Publication date: January 1, 2015Applicant: FlipChip International, LLCInventors: Eugene A. Stout, Douglas M. Scott, Anthony P. Curtis, Theodore G. Tessier, Guy F. Burgess
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Patent number: 8686556Abstract: A process for forming a heat sink on a semiconductor package at the wafer level stage of manufacture is disclosed. A semiconductor component wafer, prior to separation into separate component packages, is covered on one side with a resin metal foil layer. The resin foil layer is patterned by laser ablation to define the heat sink locations, and then a thermal paste is applied over the patterned layer. The thermal conductive paste is hardened to form the heat sinks. The wafer can then be separated into packages.Type: GrantFiled: October 4, 2012Date of Patent: April 1, 2014Assignee: FlipChip International, LLCInventors: David Clark, Theodore G. Tessier
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Publication number: 20110003470Abstract: In wafer-level chip-scale packaging and flip-chip packaging and assemblies, a solder cap is formed on a vertical pillar. In one embodiment, the vertical pillar overlies a semiconductor substrate. A solder paste, which may be doped with at least one trace element, is applied on a top surface of the pillar structure. A reflow process is performed after applying the solder paste to provide the solder cap.Type: ApplicationFiled: June 30, 2010Publication date: January 6, 2011Applicant: FlipChip International, LLCInventors: Guy F. Burgess, Anthony Curtis, Michael E. Johnson, Gene Stout, Theodore G. Tessier
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Patent number: 7091469Abstract: An optoelectronic sensor is attached to an optically transparent substrate, such as glass, and encapsulated to form an optoelectronic device. An optical assembly can be mounted opposite the optoelectronic sensor. Filters and refractive index matching materials may be included between the optoelectronic sensor and the optically transparent substrate.Type: GrantFiled: May 20, 2004Date of Patent: August 15, 2006Assignee: ST Assembly Test Services Ltd.Inventors: Dean Paul Kossives, Kambhampati Ramakrishna, Edward Lap Zak Law, Diane Sahakian, Theodore G. Tessier, Jamin Ling
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Patent number: 6022761Abstract: A method for connecting substrates includes using an adhesive interposer structure (11) to bond a semiconductor device (26) to a substrate (18). The adhesive interposer structure (11) includes a non-conductive adhesive laminant (12) and conductive adhesive bumps (13). The conductive adhesive bumps (13) provide a conductive path between conductive bumps (27) on the semiconductor device (26) and conductive metal pads (21) located on the substrate (18). In an alternative embodiment, a conductive adhesive material (34) is screen or stencil printed into vias (39) located on a printed circuit board (38) to form conductive adhesive bumps (33). A non-conductive adhesive (52) is then screen or stencil printed onto the printed circuit board (38) adjacent the conductive adhesive bumps (33). A semiconductor die is then connected to the structure.Type: GrantFiled: May 28, 1996Date of Patent: February 8, 2000Assignee: Motorola, Inc.Inventors: Melissa E. Grupen-Shemansky, Jong-Kai Lin, Theodore G. Tessier
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Patent number: 5892661Abstract: A smartcard (10) is formed in part by a laminate layer (77). The laminate layer (77) is made up of a plurality of dielectric layers (11,30), insulating layers (45, 50), resistive layers (55), and electrically active structures. The electrically active structures include a capacitive structure (23) which is formed from one of the dielectric layers (11) and an antennae (32) which is made from a conductive layer that is formed into a spiral pattern on the another dielectric layer (30). These layers (11,30, 45, 50, 55) are formed separately and then pressed together to form the laminate layer (77).Type: GrantFiled: October 31, 1996Date of Patent: April 6, 1999Assignee: Motorola, Inc.Inventors: John W. Stafford, Theodore G. Tessier, David A. Jandzinski
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Patent number: 5789815Abstract: A three dimensional packaging approach reduces the overall footprint for interconnecting multiple semiconductor die. An three-dimensional folded module (10) produces a final package having a footprint size reduced by an approximate factor of four when compared to conventional electronic packaging. The module has a protective covering such as a cap (62) or a sealant (64) as a moisture barrier. Thus, high integration using flexible appendages (15, 25, 35, and 45) attached to a rigid substrate (12) and singularly folded above the substrate (12) results in both a small footprint package and also a light package. A reel-to-reel flex tape (56) assembly provides pre-tested flex boards (16, 26, 36, and 46) resulting in a cost-effective manufacturable package for semiconductor components.Type: GrantFiled: April 23, 1996Date of Patent: August 4, 1998Assignee: Motorola, Inc.Inventors: Theodore G. Tessier, John W. Stafford, David A. Jandzinski
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Patent number: 5661088Abstract: A method of packaging an electronic component includes forming a hole (24) in a substrate (21) having a first surface (22) opposite a second surface (23) and disposing and patterning a malleable layer (26) over the first surface (22) and over the hole (24) of the substrate (21). The malleable layer (26) has a third surface (27) opposite a fourth surface (28). A portion (29) of the fourth surface (28) is exposed by the hole (24) in the substrate (21). An electrically conductive layer is simultaneously disposed over the portion (29) of the fourth surface (28) and over a different portion of the third surface (27) of the malleable layer (26). The malleable layer (26) is deformed into the hole (24). Then, a semiconductor die (43) is coupled to the malleable layer (26), and an underencapsulant (37) is disposed under the semiconductor die (43) and over the hole (24).Type: GrantFiled: January 11, 1996Date of Patent: August 26, 1997Assignee: Motorola, Inc.Inventors: Theodore G. Tessier, Kenneth Kaskoun, David A. Jandzinski
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Patent number: 5221426Abstract: An improved laser etch-back process forms a metal feature on an area of a polymeric or other non-metallic substrate. The process comprises forming a metal layer on the area that includes a first, relatively thick section, and a second, relatively thin section. Thereafter, the metal layer is uniformly irradiated with a laser pulse, but not to vaporize metal from the thick section. Thus, the laser pulse selectively etches the thin section to remove the metal and expose the substrate, without disturbing the thick section, which forms the desired metal feature.Type: GrantFiled: November 29, 1991Date of Patent: June 22, 1993Assignee: Motorola Inc.Inventors: Theodore G. Tessier, John W. Stafford, William F. Hoffman
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Patent number: 5217568Abstract: A process for etching a silicon substrate to form a feature such as a V-groove, utilizes a coating formed of an alkaline resistance polymer. A preferred polymer is poly(benzocyclobutene) resin. The coating is applied to the substrate and removed form a selected region whereupon the underlying silicon is etched with an alkaline solution. In one aspect, an optical fiber is inserted in the etched groove and coupled to an optical waveguide embedded within the coating.Type: GrantFiled: February 3, 1992Date of Patent: June 8, 1993Assignee: Motorola, Inc.Inventors: Theodore G. Tessier, Scott Lindsey