Patents by Inventor Theodore J. Bohizic
Theodore J. Bohizic has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9158566Abstract: Dynamic creation of a spatially aware emulation environment comprising Host cells of Host pages corresponding to Guest cells of Guest pages of Guest instructions. Each Host cell comprises a semantic routine for emulating a corresponding Guest instruction located at the corresponding Guest cell of the guest page.Type: GrantFiled: November 13, 2012Date of Patent: October 13, 2015Assignee: International Business Machines CorporationInventors: Theodore J Bohizic, Reid T Copeland, Marcel Mitran, Ali I Sheikh
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Patent number: 8949106Abstract: A selected group of Guest machine instructions in an emulation environment are translated to a semantic routine of Host machine instructions, wherein Guest cells corresponding to an opcode portion of a Guest instruction are mapped to corresponding Host cells, wherein the semantic routine of Host machine instructions are patched into a Host cell corresponding to the first Guest cell of the group of Guest machine instructions, wherein other Host cells of the corresponding Host cells are patched with semantic routines for emulating single instructions associated with the corresponding Guest cell.Type: GrantFiled: September 18, 2009Date of Patent: February 3, 2015Assignee: International Business Machines CorporationInventors: Theodore J. Bohizic, Reid T. Copeland, Marcel Mitran, Ali I. Sheikh
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Patent number: 8875114Abstract: Optimizations are provided for processing environments. Selected memory objects are tagged with unique identifiers by an operating system of the environment, and those identifiers are used to manage processing within the environment. By detecting by a processing platform of the environment that a memory object has been tagged with a unique identifier, certain tasks may be bypassed and/or memory objects may be reused, even if located at a different location.Type: GrantFiled: September 21, 2007Date of Patent: October 28, 2014Assignee: International Business Machines CorporationInventors: Theodore J. Bohizic, Rahul Chandrakar, Mark H. Decker, Viktor S. Gyuris
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Patent number: 8768683Abstract: A plurality of Guest cells of Guest instructions are provided with corresponding Host cells for emulating Guest instructions, each Guest instruction having a Guest cell corresponding to a Host cell. Each of the Host cells are initialized with an initialization routine for discovering a corresponding semantic routine for emulating the Guest instruction. When an instruction is to be emulated for the first time, the initialization routine patches itself with the discovered semantic routine such that subsequent emulation of the Guest instruction can be directly performed.Type: GrantFiled: April 19, 2013Date of Patent: July 1, 2014Assignee: International Business Machines CorporationInventors: Theodore J Bohizic, Reid T Copeland, Marcel Mitran, Ali I Sheikh
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Publication number: 20140136179Abstract: Dynamic creation of a spatially aware emulation environment comprising Host cells of Host pages corresponding to Guest cells of Guest pages of Guest instructions. Each Host cell comprises a semantic routine for emulating a corresponding Guest instruction located at the corresponding Guest cell of the guest page.Type: ApplicationFiled: November 13, 2012Publication date: May 15, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Theodore J Bohizic, Reid T Copeland, Marcel Mitran, Ali I Sheikh
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Publication number: 20130231913Abstract: A plurality of Guest cells of Guest instructions are provided with corresponding Host cells for emulating Guest instructions, each Guest instruction having a Guest cell corresponding to a Host cell. Each of the Host cells are initialized with an initialization routine for discovering a corresponding semantic routine for emulating the Guest instruction.Type: ApplicationFiled: April 19, 2013Publication date: September 5, 2013Applicant: International Business Machines CorporationInventors: Theodore J. Bohizic, Reid T. Copeland, Marcel Mitran, Ali I. Sheikh
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Patent number: 8447583Abstract: A plurality of Guest cells of Guest instructions are provided with corresponding Host cells for emulating Guest instructions, each Guest instruction having a Guest cell corresponding to a Host cell. Each of the Host cells are initialized with an initialization routine for discovering a corresponding semantic routine for emulating the Guest instruction. When an instruction is to be emulated for the first time, the initialization routine patches itself with the discovered semantic routine such that subsequent emulation of the Guest instruction can be directly performed.Type: GrantFiled: September 18, 2009Date of Patent: May 21, 2013Assignee: International Business Machines CorporationInventors: Theodore J. Bohizic, Reid T. Copeland, Marcel Mitran, Ali I. Sheikh
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Patent number: 8438340Abstract: A disjoint instruction for accessing operands in memory while executing in a processor of a plurality of processes interrogates a state indicator settable by other processors to determine if the disjoint instruction accessed the operands without an intervening store operation from another processor to the operand. A condition code is set based on the state indicator.Type: GrantFiled: February 18, 2010Date of Patent: May 7, 2013Assignee: International Business Machines CorporationInventors: Theodore J. Bohizic, Reid T. Copeland, Marcel Mitran
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Patent number: 8428930Abstract: Dynamic creation of a spatially aware emulation environment comprising Host cells of Host pages corresponding to Guest cells of Guest pages of Guest instructions. Each Host cell comprises a semantic routine for emulating a corresponding Guest instruction located at the corresponding Guest cell of the guest page.Type: GrantFiled: September 18, 2009Date of Patent: April 23, 2013Assignee: International Business Machines CorporationInventors: Theodore J. Bohizic, Reid T. Copeland, Marcel Mitran, Ali I. Sheikh
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Patent number: 8364461Abstract: Native code corresponding to an invalidated trace is re-used in a system emulator. A first trace is identified. A dropped second trace is identified. The dropped second trace is associated with a first native code for emulating the second trace. If the identified first trace corresponds to the dropped second trace, the first native code is associated to the first trace, and the first native code is executed. If the identified first trace does not correspond to the dropped second trace, a second native code for emulating the first trace is created, the second native code is associated with the first trace, and the second native code is executed.Type: GrantFiled: November 9, 2009Date of Patent: January 29, 2013Assignee: International Business Machines CorporationInventors: Theodore J Bohizic, Reid T Copeland, Ali Sheikh, Kirk A Stewart
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Patent number: 8301434Abstract: A instructions of a Guest program to be emulated by a Host computer occupy one or more Guest cells of Guest memory, each Guest cell having a corresponding Host cell in Host memory. The emulator selects a Host cell for emulating a Guest instruction. When the Host cell corresponds to a Guest cell other than a cell aligned with the beginning of the Guest instruction, a wild branch handling routine is executed.Type: GrantFiled: September 18, 2009Date of Patent: October 30, 2012Assignee: International Buisness Machines CorporationInventors: Theodore J. Bohizic, Reid T. Copeland, Marcel Mitran, Ali I. Sheikh
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Patent number: 8099274Abstract: An article of manufacture, method and system are provided for facilitating input/output (I/O) processing of at least one guest processing system. The article of manufacture includes at least one computer-usable medium having computer-readable program code logic to facilitate the I/O processing of the at least one guest processing system. The computer-readable program code logic when executing performing the following: emulating on a native system an I/O architecture for the at least one guest processing system, the emulating including: providing multiple device managers for a plurality of I/O devices of the I/O architecture; providing at least one communications adapter process interfacing the multiple device managers to the at least one network driver process; and wherein the multiple device managers translate I/O messages in at least one guest processing system format to messages in native system format for processing by the at least one communications adapter process, thereby facilitating I/O processing.Type: GrantFiled: March 30, 2007Date of Patent: January 17, 2012Assignee: International Business Machines CorporationInventors: Theodore J. Bohizic, Richard T. Brandle, Ping T. Chan, Michael S. Cirulli, Paul M. Gioquindo, Ying-Yeung Li, Stephen R. Valley
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Publication number: 20110202729Abstract: A disjoint instruction for accessing operands in memory while executing in a processor of a plurality of processes interrogates a state indicator settable by other processors to determine if the disjoint instruction accessed the operands without an intervening store operation from another processor to the operand. A condition code is set based on the state indicator.Type: ApplicationFiled: February 18, 2010Publication date: August 18, 2011Applicant: International Business Machines CorporationInventors: Theodore J. Bohizic, Reid T. Copeland, Marcel Mitran
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Publication number: 20110112820Abstract: Native code corresponding to an invalidated trace is re-used in a system emulator. A first trace is identified. A dropped second trace is identified. The dropped second trace is associated with a first native code for emulating the second trace. If the identified first trace corresponds to the dropped second trace, the first native code is associated to the first trace, and the first native code is executed. If the identified first trace does not correspond to the dropped second trace, a second native code for emulating the first trace is created, the second native code is associated with the first trace, and the second native code is executed.Type: ApplicationFiled: November 9, 2009Publication date: May 12, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Theodore J Bohizic, Reid Copeland, Ali Sheikh, Kirk A. Stewart
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Patent number: 7917326Abstract: A technique for estimating and improving the test coverage for large machines, while accumulating minimum information of past test cases (i.e., minimum feedback) is provided. The technique is scalable in the sense that the number of machine instructions needed to measure the test coverage can range from a few instructions to all the instructions. The technique is easily integrated into existing test generation systems and is applicable to both uni- and multi-processing systems.Type: GrantFiled: January 30, 2008Date of Patent: March 29, 2011Assignee: International Business Machines CorporationInventors: Theodore J. Bohizic, Ali Y. Duale, Dennis W. Wittig
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Publication number: 20110071815Abstract: A instructions of a Guest program to be emulated by a Host computer occupy one or more Guest cells of Guest memory, each Guest cell having a corresponding Host cell in Host memory. The emulator selects a Host cell for emulating a Guest instruction. When the Host cell corresponds to a Guest cell other than a cell aligned with the beginning of the Guest instruction, a wild branch handling routine is executed.Type: ApplicationFiled: September 18, 2009Publication date: March 24, 2011Applicant: International Business Machines CorporationInventors: Theodore J. Bohizic, Reid T. Copeland, Marcel Mitran, Ali I. Sheikh
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Publication number: 20110071816Abstract: A selected group of Guest machine instructions in an emulation environment are translated to a semantic routine of Host machine instructions, wherein Guest cells corresponding to an opcode portion of a Guest instruction are mapped to corresponding Host cells, wherein the semantic routine of Host machine instructions are patched into a Host cell corresponding to the first Guest cell of the group of Guest machine instructions, wherein other Host cells of the corresponding Host cells are patched with semantic routines for emulating single instructions associated with the corresponding Guest cell.Type: ApplicationFiled: September 18, 2009Publication date: March 24, 2011Applicant: International Business Machines CorporationInventors: Theodore J. Bohizic, Reid T. Copeland, Marcel Mitran, Ali I. Sheikh
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Publication number: 20110071814Abstract: A plurality of Guest cells of Guest instructions are provided with corresponding Host cells for emulating Guest instructions, each Guest instruction having a Guest cell corresponding to a Host cell. Each of the Host cells are initialized with an initialization routine for discovering a corresponding semantic routine for emulating the Guest instruction.Type: ApplicationFiled: September 18, 2009Publication date: March 24, 2011Applicant: International Business Machines CorporationInventors: Theodore J. Bohizic, Reid T. Copeland, Marcel Mitran, Ali I. Sheikh
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Publication number: 20110071813Abstract: Dynamic creation of a spatially aware emulation environment comprising Host cells of Host pages corresponding to Guest cells of Guest pages of Guest instructions. Each Host cell comprises a semantic routine for emulating a corresponding Guest instruction located at the corresponding Guest cell of the guest page.Type: ApplicationFiled: September 18, 2009Publication date: March 24, 2011Applicant: International Business Machines CorporationInventors: Theodore J. Bohizic, Reid T. Copeland, Marcel Mitran, Ali I. Sheikh
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Patent number: 7904270Abstract: A technique for estimating and improving the test coverage for large machines, while accumulating minimum information of past test cases (i.e., minimum feedback) is provided. The technique is scalable in the sense that the number of machine instructions needed to measure the test coverage can range from a few instructions to all the instructions. The technique is easily integrated into existing test generation systems and is applicable to both uni- and multi-processing systems.Type: GrantFiled: January 30, 2008Date of Patent: March 8, 2011Assignee: International Business Machines CorporationInventors: Theodore J. Bohizic, Ali Y. Duale, Dennis W. Wittig