Abstract: Apparatuses and methods for performing concurrent memory access operations for different memory planes are disclosed herein. An example apparatus may include a memory array having a plurality of memory planes. Each of the plurality of memory planes comprises a plurality of memory cells. The apparatus may further include a controller configured to receive a group of memory command and address pairs. Each memory command and address pair of the group of memory command and address pairs may be associated with a respective memory plane of the plurality of memory planes. The internal controller may be configured to concurrently perform memory access operations associated with each memory command and address pair of the group of memory command and address pairs regardless of page types associated with the pairs of the group (e.g., even if two or more of the memory command and address pairs may be associated with different page types).

Abstract: Embodiments are provided for protecting boot block space in a memory device. Such a memory device may include a memory array having a protected portion and a serial interface controller. The memory device may have a register that enables or disables access to the portion when data indicating whether to enable or disable access to the portion is written into the register via a serial data in (SI) input.

Abstract: A memory device includes a memory array and control logic, operatively coupled with the memory array, to perform operations including causing a first current to be obtained with respect to cells of a wordline maintained at a first voltage, determining that the cells are at a second voltage lower than the first voltage, in response to determining that the cells are the second voltage, causing a voltage ramp down process to be initiated, causing a second current to be sampled with respect to the cells during the voltage ramp down process, and detecting an existence of charge loss by determining whether the second current satisfies a threshold condition in view of the first current.

Abstract: Memory devices are provided that include special operating modes accessible upon receipt of a particular message from a host. One device includes a memory array, a special mode enable register, and a controller. When the controller receives a register write command to write first data into the special mode enable register and the memory device does so, the memory device operates in a first mode. When the controller receives a register write command to write second data into the special mode enable register and the memory device does so, the memory device operates in a second mode.

Abstract: A memory device includes a memory array comprising a first number of planes, a second number of independent plane driver circuits, wherein the second number is less than the first number, and a plane selection circuit to couple the second number of independent plane driver circuits to the first number of planes of the memory array. The memory device further includes control logic, to perform receive a first read command and identify, among the first number of planes, a first plane to which the first read command is directed. The control logic further configures the plane selection circuit to couple a first independent plane driver of the second number of independent plane drivers to the first plane and causes the first independent plane driver to perform a first read operation corresponding to the first read command on the first plane.

Abstract: Memory devices are provided that include special operating modes accessible upon receipt of a particular message from a host. One device includes a memory array, a special mode enable register, and a controller. When the controller receives a register write command to write first data into the special mode enable register and the memory device does so, the memory device operates in a first mode. When the controller receives a register write command to write second data into the special mode enable register and the memory device does so, the memory device operates in a second mode.

Abstract: A memory device includes a memory array with memory blocks each having a plurality of memory cells, and one or more current monitors configured to measure current during post-deployment operation of the memory device; and a controller configured to identify a bad block within the memory blocks based on the measured current, and disable the bad block for preventing access thereof during subsequent operations of the memory device.

Abstract: A resistor-capacitor (RC) sensor circuit includes an integration capacitor configured to integrate a representative copy of a current that drives an electronic circuit line. The integration capacitor is configured to integrate over a first time period to generate a first representative voltage and over a second time period to generate a second representative voltage. The RC sensor circuit includes a sampling circuit coupled to the integration capacitor and configured to sample the first representative voltage and the second representative voltage. A ratio of the first sampled voltage and the second sampled voltage is indicative of an RC time constant of the electronic circuit line.

Abstract: Apparatuses and methods for performing concurrent memory access operations for different memory planes are disclosed herein. An example apparatus may include a memory array having a plurality of memory planes. Each of the plurality of memory planes comprises a plurality of memory cells. The apparatus may further include a controller configured to receive a group of memory command and address pairs. Each memory command and address pair of the group of memory command and address pairs may be associated with a respective memory plane of the plurality of memory planes. The internal controller may be configured to concurrently perform memory access operations associated with each memory command and address pair of the group of memory command and address pairs regardless of page types associated with the pairs of the group (e.g., even if two or more of the memory command and address pairs may be associated with different page types).

Abstract: Control logic in a memory device initiates a read operation on a memory array of the memory device and performs a calibration operation to detect a change in string resistance in the memory array. The control logic determines whether the change in string resistance is attributable to charge loss in the memory array, and responsive to determining that the change in string resistance is attributable to charge loss in the memory array, preforms the read operation using calibrated read voltage levels to read data from the memory array.

Abstract: Apparatuses and methods including multiple read modes for reading data from a memory are described. An example apparatus includes a memory including a first read mode and a second read mode. The memory has a read operation for the first read mode including a first pre-access phase, an access phase, and a first post-access phase. The read operation for the second read mode includes a second pre-access phase, the access phase, and a second post-access phase. The read operation for either the first read mode or the second read mode is performed responsive to the memory receiving a read command. The second pre-access phase is different from the first pre-access phase, with the second pre-access phase having a shorter time than the first pre-access phase measured from receipt of the read command.

Abstract: A memory device includes a memory array and control logic, operatively coupled with the memory array, to perform operations including causing a first current to be obtained with respect to cells of a wordline maintained at a first voltage, determining that the cells are at a second voltage lower than the first voltage, in response to determining that the cells are the second voltage, causing a voltage ramp down process to be initiated, causing a second current to be sampled with respect to the cells during the voltage ramp down process, and detecting an existence of charge loss by determining whether the second current satisfies a threshold condition in view of the first current.

Abstract: A memory device includes a memory array comprising a first number of planes, a second number of independent plane driver circuits, wherein the second number is less than the first number, and a plane selection circuit to couple the second number of independent plane driver circuits to the first number of planes of the memory array. The memory device further includes control logic, to perform receive a first read command and identify, among the first number of planes, a first plane to which the first read command is directed. The control logic further configures the plane selection circuit to couple a first independent plane driver of the second number of independent plane drivers to the first plane and causes the first independent plane driver to perform a first read operation corresponding to the first read command on the first plane.

Abstract: Arrays of memory cells including an isolation region between first and second access lines, a first memory cell having a control gate in contact with the first access line and a charge storage node having a curved cross-section having a first end in contact with a first portion of the isolation region on a first side of the isolation region and a second end in contact with a second portion of the isolation region on the isolation region's first side, and a second memory cell having a control gate in contact with the second access line and a charge storage node having a curved cross-section having a first end in contact with the first portion of the isolation region on a second side of the isolation region and a second end in contact with the second portion of the isolation region on the isolation region's first side.

Abstract: Apparatuses and methods for performing concurrent memory access operations for different memory planes are disclosed herein. An example apparatus may include a memory array having a plurality of memory planes. Each of the plurality of memory planes comprises a plurality of memory cells. The apparatus may further include a controller configured to receive a group of memory command and address pairs. Each memory command and address pair of the group of memory command and address pairs may be associated with a respective memory plane of the plurality of memory planes. The internal controller may be configured to concurrently perform memory access operations associated with each memory command and address pair of the group of memory command and address pairs regardless of page types associated with the pairs of the group (e.g., even if two or more of the memory command and address pairs may be associated with different page types).

Abstract: Apparatuses and methods including multiple read modes for reading data from a memory are described. An example apparatus includes a memory including a first read mode and a second read mode. The memory has a read operation for the first read mode including a first pre-access phase, an access phase, and a first post-access phase. The read operation for the second read mode includes a second pre-access phase, the access phase, and a second post-access phase. The read operation for either the first read mode or the second read mode is performed responsive to the memory receiving a read command. The second pre-access phase is different from the first pre-access phase, with the second pre-access phase having a shorter time than the first pre-access phase measured from receipt of the read command.

Abstract: Arrays of memory cells including pairs of memory cells having respective control gates connected to respective access lines, and having respective charge storage nodes between the respective access lines.

Abstract: A memory device includes a memory array comprising a plurality of wordlines and a regulator circuit selectively coupled to the plurality of wordlines, wherein the regulator circuit is configured to perform a detection routine to sample a load current from a selected wordline of the plurality of wordlines and generate a measured output voltage, wherein the measured output voltage modulates with respect to the load current. The memory device further includes a comparator circuit coupled to the regulator circuit, wherein the comparator circuit is configured to generate a comparison result based on a difference between the measured output voltage and a reference voltage and a local media controller coupled to the comparator circuit, wherein the local media controller is configured to identify a presence of a defect on the selected wordline in response to the comparison result satisfying a threshold condition.

Abstract: Embodiments are provided for protecting boot block space in a memory device. Such a memory device may include a memory array having a protected portion and a serial interface controller. The memory device may have a register that enables or disables access to the portion when data indicating whether to enable or disable access to the portion is written into the register via a serial data in (SI) input.

Abstract: Methods of operating apparatus, as well as apparatus configured to perform such methods, include checking whether power loss to the apparatus during programming of user data to a grouping of memory cells of the apparatus is indicated, and, when power loss is indicated, checking feature settings of the apparatus to determine a location of the apparatus containing an address of the grouping of memory cells, and recovering the address of the grouping of memory cells from the determined location.