Abstract: Embodiments of the invention include a semiconductor structure including a light emitting layer disposed between an n-type region and a p-type region. A metal n-contact is connected to the n-type region. A metal p-contact is in direct contact with the p-type region. An interconnect is electrically connected to one of the n-contact and the p-contact. The interconnect is disposed adjacent to the semiconductor structure.

Abstract: Embodiments of the invention include a semiconductor structure including a light emitting layer disposed between an n-type region and a p-type region. A metal n-contact is connected to the n-type region. A metal p-contact is in direct contact with the p-type region. An interconnect is electrically connected to one of the n-contact and the p-contact. The interconnect is disposed adjacent to the semiconductor structure.

Abstract: Embodiments of the invention include a semiconductor structure including a light emitting layer disposed between an n-type region and a p-type region. A metal n-contact is connected to the n-type region. A metal p-contact is in direct contact with the p-type region. An interconnect is electrically connected to one of the n-contact and the p-contact. The interconnect is disposed adjacent to the semiconductor structure.

Abstract: Embodiments of the invention include a semiconductor structure including a light emitting layer disposed between an n-type region and a p-type region. A metal n-contact is connected to the n-type region. A metal p-contact is in direct contact with the p-type region. An interconnect is electrically connected to one of the n-contact and the p-contact. The interconnect is disposed adjacent to the semiconductor structure.

Abstract: A silicon-on-insulator substrate and its method of formation are disclosed. In another embodiment, a method for forming a high-k gate dielectric is disclosed. The silicon-on-insulator substrate is prepared by forming a lattice matched dielectric layer (20) over a semiconductor substrate (10). A thermodynamically stable dielectric layer (22) is then formed over the lattice matched dielectric layer (20). A semiconductor layer (30) is then formed over the thermodynamically stable dielectric layer (22). Formation of the high-k gate dielectric includes the processing steps used to form the silicon-on-insulator substrate and additionally includes bonding a second semiconductor substrate (50) to the semiconductor layer (30). The first semiconductor substrate (10) is then removed to expose the lattice matched dielectric layer (20). This results in a silicon substrate that has a layer of high-k dielectric material that can be used as the gate dielectric for integrated circuits formed on the substrate.