Patents by Inventor Theresia Bauer

Theresia Bauer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7407891
    Abstract: Semiconductor wafers are leveled by position-dependent measurement of a wafer-characterizing parameter to determine the position-dependent value of this parameter over an entire surface of the semiconductor wafer, etching the entire surface of the semiconductor wafer simultaneously under the action of an etching medium with simultaneous illumination of the entire surface, the material-removal etching rate dependent on the light intensity at the surface of the semiconductor wafer, the light intensity being established in a position-dependent manner such that the differences in the position-dependent values of the parameter measured in step a) are reduced by the position-dependent material-removal rate. Semiconductor wafers with improved flatness and nanotopography, and SOI wafers with improved layer thickness homogeneity are produced by this process.
    Type: Grant
    Filed: November 7, 2005
    Date of Patent: August 5, 2008
    Assignee: Siltronic AG
    Inventors: Theresia Bauer, Robert Hoelzl, Andreas Huber, Reinhold Wahlich
  • Publication number: 20060097355
    Abstract: Semiconductor wafers are leveled by a) position-dependent measurement of a wafer-characterizing parameter to determine the position-dependent value of this parameter over an entire surface of the semiconductor wafer, b) etching the entire surface of the semiconductor wafer simultaneously under the action of an etching medium with simultaneous illumination of the entire surface, the material-removal etching rate dependent on the light intensity at the surface of the semiconductor wafer, the light intensity being established in a position-dependent manner such that the differences in the position-dependent values of the parameter measured in step a) are reduced by the position-dependent material-removal rate, semiconductor wafers with improved flatness and nanotopography and SOI wafer with improved layer thickness homogeneity are achieved. An apparatus for carrying out the method is also disclosed.
    Type: Application
    Filed: November 7, 2005
    Publication date: May 11, 2006
    Applicant: Siltronic AG
    Inventors: Theresia Bauer, Robert Hoelzl, Andreas Huber, Reinhold Wahlich
  • Publication number: 20030129834
    Abstract: A semiconductor wafer has a front side 1, a back side 2, a top layer 3, a bottom layer 4, an upper inner layer 5 lying below the top layer 3, a lower inner layer 6 lying above the bottom layer 4, a central region 7 between the layers 5 and 6 and an uneven distribution of crystal lattice defects. The concentration of the defects exhibits a first maximum (max1) in the central region 7 and a second maximum (max2) in the bottom layer 4.
    Type: Application
    Filed: May 19, 2000
    Publication date: July 10, 2003
    Inventors: Dr. Gunther Obermeier, Reinhold Wahlich, Dr. Theresia Bauer, Alfred Buchner
  • Patent number: 6579589
    Abstract: A semiconductor wafer has a front side 1, a back side 2, a top layer 3, a bottom layer 4, an upper inner layer 5 lying below the top layer 3, a lower inner layer 6 lying above the bottom layer 4, a central region 7 between the layers 5 and 6 an uneven distribution of crystal lattice defects. The concentration of the defects exhibits a first maximum (max1) in the central region 7 and a second maximum (max2) in the bottom layer 4.
    Type: Grant
    Filed: May 19, 2000
    Date of Patent: June 17, 2003
    Assignee: Wackersiltronic Gesellschaft fur Halbleitermaterialien AG
    Inventors: Günther Obermeier, Reinhold Wahlich, Theresia Bauer, Alfred Buchner
  • Patent number: 6395653
    Abstract: A semiconductor wafer has a front side 1, a back side 2, a top layer 3, a bottom layer 4, an upper inner layer 5 lying beneath the top layer 3, an lower inner layer 6 lying above the bottom layer 4, a central region 7 between the layers 5 and 6, and an uneven distribution of crystal lattice defects. The crystal lattice defects are substitutionally or interstitially included nitrogen or vacancies.
    Type: Grant
    Filed: May 22, 2000
    Date of Patent: May 28, 2002
    Assignee: Wacker Siltronic Gesellschaft für Halbleitermaterialien AG
    Inventors: Gunther Obermeier, Alfred Buchner, Theresia Bauer, Jürgen Hage, Rasso Ostermeir, Wilfried Von Ammon
  • Publication number: 20020008098
    Abstract: A process for the heat treatment of semiconductor wafers, preferably monocrystalline ultrapure silicon wafers, using an upper and a lower heat source, which can be a plurality of upper and a plurality of lower lamps or banks of lamps. In the process chamber of an RTP system, the heat treatment is carried out on at least two wafers which are arranged parallel above one another, spaced apart, and are identical in terms of geometrical dimensions and thermal material properties.
    Type: Application
    Filed: August 23, 1999
    Publication date: January 24, 2002
    Inventors: ALFRED BUCHNER, THOMAS TEUSCHLER, JOHANN SPERL, THERESIA BAUER
  • Patent number: 6309467
    Abstract: Semiconductor material has a low metal concentration at the surface. The semiconductor material has an iron content and/or chromium content on the surface of less than 6.66×10−11 g/cm2. A method for producing this semiconductor material includes a preliminary cleaning, a main cleaning and hydrophilization. A device for use in this method has a container with pyramid-shaped recesses at the bottom.
    Type: Grant
    Filed: September 15, 1998
    Date of Patent: October 30, 2001
    Assignee: Wacker-Chemie GmbH
    Inventors: Hanns Wochner, Theresia Bauer, Josef Dietl, Werner Ott, Herbert Pichler, Wilhelm Schmidbauer, Dieter Seifert, Susanne Weizbauer
  • Patent number: 6046117
    Abstract: A process is taught for etching semiconductor wafers with an etching mixture comprising nitric and hydrofluoric acids and optionally a surfactant. To this mixture are added either more hydrofluoric acid, or more hydrofluoric and nitric acids, with the added acids having concentrations of at least 70% by weight. The use of concentrated acids reduces the loss of substrate material and extends etching bath life.
    Type: Grant
    Filed: May 21, 1998
    Date of Patent: April 4, 2000
    Assignee: Wacker Siltronic Gesellschaft Fur Halbleitermaterialien AG
    Inventors: Theresia Bauer, Susanne Weizbauer, Hanns Wochner, Alfred Bergler