Abstract: A method of manufacturing a microelectronic device may include forming a wiring layer on a first surface of a wafer. The method may also include forming a modified layer along separation regions for each microelectronic device of the wafer by focusing a laser on an inside portion of the wafer. The method may also include removing material from the second surface of the wafer. The wafer may be cooled to a temperature where a low dielectric constant layer extending across the separation regions is brittle while the material is removed from the second surface of the wafer. The method may further include separating the wafer along the separation region to form separate microelectronic devices.

Abstract: A method of manufacturing a microelectronic device may include forming a wiring layer on a first surface of a wafer. The method may also include forming a modified layer along separation regions for each microelectronic device of the wafer by focusing a laser on an inside portion of the wafer. The method may also include removing material from the second surface of the wafer. The wafer may be cooled to a temperature where a low dielectric constant layer extending across the separation regions is brittle while the material is removed from the second surface of the wafer. The method may further include separating the wafer along the separation region to form separate microelectronic devices.

Abstract: A three-dimensional model of a reconstructed bone framework is obtained using an iterative, surface interpolating algorithm. A reference and a target three-dimensional model are provided. The reference model is non-rigidly registered to the target model based upon positional constraints, so as to produce a registered reference model. An initial reconstructed model is set as the registered reference model. A first correspondence search is iteratively conducted to identify a first set of corresponding points on the reconstructed and target models. During each iteration, the reconstructed model is incrementally and non-rigidly registered to the target model based upon the corresponding points. A second correspondence search is conducted to identify a second set of corresponding points on the reconstructed and target models.

Abstract: A three-dimensional model of a reconstructed bone framework is obtained using an iterative, surface interpolating algorithm. A reference and a target three-dimensional model are provided. The reference model is non-rigidly registered to the target model based upon positional constraints, so as to produce a registered reference model. An initial reconstructed model is set as the registered reference model. A first correspondence search is iteratively conducted to identify a first set of corresponding points on the reconstructed and target models. During each iteration, the reconstructed model is incrementally and non-rigidly registered to the target model based upon the corresponding points. A second correspondence search is conducted to identify a second set of corresponding points on the reconstructed and target models.

Abstract: Methods of fabricating a semiconductor device package may involve providing a fan out wafer including semiconductor-device-package locations at a base level. Laterally offset semiconductor dice may be stacked at least some semiconductor-device-package locations of the fan out wafer to expose bond pads at a lateral periphery of each of the laterally offset semiconductor dice. The laterally offset semiconductor dice may be electrically connected to one another and associated electrically conductive traces of the at least some semiconductor-device-package locations. The semiconductor-device-package locations having stacks of semiconductor dice thereon may be singulated from the fan out wafer.

Abstract: Methods of fabricating a semiconductor device package may involve providing a fan out wafer including semiconductor-device-package locations at a base level. Laterally offset semiconductor dice may be stacked at least some semiconductor-device-package locations of the fan out wafer to expose bond pads at a lateral periphery of each of the laterally offset semiconductor dice. The laterally offset semiconductor dice may be electrically connected to one another and associated electrically conductive traces of the at least some semiconductor-device-package locations. The semiconductor-device-package locations having stacks of semiconductor dice thereon may be singulated from the fan out wafer.

Abstract: Methods of making semiconductor device packages may involve providing a fan out wafer including semiconductor-device-package locations. Each semiconductor-device-package location may include at least two mutually spaced semiconductor dice and a dielectric material laterally surrounding each of the dice and extending between adjacent semiconductor-device-package locations. Electrically conductive traces may extend over active surfaces of the dice and laterally beyond peripheries of the dice over the dielectric material to locations of electrically conductive vias extending from the electrically conductive traces through the dielectric molding material. Semiconductor dice may be stacked on a side of at least some semiconductor-device-package locations of the fan out wafer opposite the electrically conductive traces. The stacks of semiconductor dice may be electrically connected to electrically conductive vias of the at least some semiconductor-device-package locations.

Abstract: Methods of making semiconductor device packages may involve providing a fan out wafer including semiconductor-device-package locations. Each semiconductor-device-package location may include at least two mutually spaced semiconductor dice and a dielectric material laterally surrounding each of the dice and extending between adjacent semiconductor-device-package locations. Electrically conductive traces may extend over active surfaces of the dice and laterally beyond peripheries of the dice over the dielectric material to locations of electrically conductive vias extending from the electrically conductive traces through the dielectric molding material. Semiconductor dice may be stacked on a side of at least some semiconductor-device-package locations of the fan out wafer opposite the electrically conductive traces. The stacks of semiconductor dice may be electrically connected to electrically conductive vias of the at least some semiconductor-device-package locations.

Abstract: A bioabsorbable plug implant, suitable for bone tissue regeneration, includes a first portion, and a second portion extending outwardly from the first portion, the first and second portions formed from expandable material. A method for bone tissue regeneration includes providing a bioabsorbable plug implant, wherein the implant has a first portion and a second portion extending outwardly from the first portion. The first and second portions are formed from expandable material. The second portion is inserted into a defect or gap of a bone. The first surface engages the outside contour of the defect or gap. The plug implant is allowed to contact body fluids, thereby expanding the size of the plug implant so that the plug fits into the defect or gap.

Abstract: A bioabsorbable plug implant, suitable for bone tissue regeneration, comprising a first portion, and a second portion extending outwardly from the first portion, the first and second portions formed from expandable material. A method for bone tissue regeneration comprising the steps of: providing a bioabsorbable plug implant, wherein the implant comprises a first portion and a second portion extending outwardly from the first portion, the first and second portions formed from expandable material; inserting the second portion into a defect or gap of a bone, the first surface engaging the outside contour of the defect or gap; allowing the plug implant to contact body fluids, thereby expanding the size of the plug implant so that the plug fits into the defect or gap.

Abstract: Semiconductor devices and stacked die assemblies, and methods of fabricating the devices and assemblies for increasing semiconductor device density are provided.

Abstract: Semiconductor devices and stacked die assemblies, and methods of fabricating the devices and assemblies are provided.

Abstract: Semiconductor devices and stacked die assemblies, and methods of fabricating the devices and assemblies for increasing semiconductor device density are provided.

Abstract: Semiconductor devices and stacked die assemblies, and methods of fabricating the devices and assemblies for increasing semiconductor device density are provided.

Abstract: Semiconductor devices and stacked die assemblies, and methods of fabricating the devices and assemblies for increasing semiconductor device density are provided.

Abstract: Semiconductor devices and stacked die assemblies, and methods of fabricating the devices and assemblies for increasing semiconductor device density are provided.

Abstract: Semiconductor devices and stacked die assemblies, and methods of fabrication are provided. In various embodiments, the die assembly comprises a first die mounted on a substrate and a second die mounted on the first die. In one embodiment, the second die has a recessed edge along the perimeter of the bottom surface to provide clearance for a bonding element extending from bond pads on the first die to pads on the substrate, thus eliminating the need for a spacer between the two dies. In another embodiment, the second die is at least partially disposed within a recess in the upper surface of the first die. In another embodiment, an adhesive element is disposed within a recess in the bottom surface of the first die for attaching the first die to the substrate. In yet another embodiment, the first die is at least partially disposed within a recess within the bottom surface of the second die. The stacked die assemblies can be encapsulated to form semiconductor packages.

Abstract: Semiconductor devices and stacked die assemblies, and methods of fabrication are provided. In various embodiments, the die assembly comprises a first die mounted on a substrate and a second die mounted on the first die. In one embodiment, the second die has a recessed edge along the perimeter of the bottom surface to provide clearance for a bonding element extending from bond pads on the first die to pads on the substrate, thus eliminating the need for a spacer between the two dies. In another embodiment, the second die is at least partially disposed within a recess in the upper surface of the first die. In another embodiment, an adhesive element is disposed within a recess in the bottom surface of the first die for attaching the first die to the substrate. In yet another embodiment, the first die is at least partially disposed within a recess within the bottom surface of the second die. The stacked die assemblies can be encapsulated to form semiconductor packages.

Abstract: Semiconductor devices and stacked die assemblies, are provided which have at least two semiconductor dies disposed on a substrate in a stacked arrangement, the first and second dies having first surfaces having bond pads, the second die having a second surface with a recessed edge portion along a perimeter of that die, and the recessed edge portion having a height sufficient for clearance of bonding elements extending from the first die.

Abstract: Semiconductor devices and stacked die assemblies, and methods of fabricating the devices and assemblies for increasing semiconductor device density are provided.