Abstract: A split memory bank may comprise a number of memory matrices forming a memory bank and a shift register in which the shift register physically separates the matrices. An integrated circuit may comprise a number of shift registers and a plurality of memory matrices forming a memory bank in which the matrices are spatially separated by the shift register. An integrated printhead may comprise a number of memory banks each comprising a plurality of memory matrices and a number of shift registers in which each shift register spatially separates a number of the matrices.

Abstract: In an example implementation, a grounding structure includes a perimeter ground line around the perimeter of a printhead die, and having north, south, east, and west segments. The structure includes an inter-slot ground line extending from the north segment to the south segment between two fluid slots, and an alternative ground line extending from the east segment to the west segment and intersecting the inter-slot ground line in a connection area near ends of the fluid slots.

Abstract: A split memory bank may comprise a number of memory matrices forming a memory bank and a shift register in which the shift register physically separates the matrices. An integrated circuit may comprise a number of shift registers and a plurality of memory matrices forming a memory bank in which the matrices are spatially separated by the shift register. An integrated printhead may comprise a number of memory banks each comprising a plurality of memory matrices and a number of shift registers in which each shift register spatially separates a number of the matrices.

Abstract: A split memory bank may comprise a number of memory matrices forming a memory bank and a shift register in which the shift register physically separates the matrices. An integrated circuit may comprise a number of shift registers and a plurality of memory matrices forming a memory bank in which the matrices are spatially separated by the shift register. An integrated printhead may comprise a number of memory banks each comprising a plurality of memory matrices and a number of shift registers in which each shift register spatially separates a number of the matrices.

Abstract: A split memory bank may comprise a number of memory matrices forming a memory bank and a shift register in which the shift register physically separates the matrices. An integrated circuit may comprise a number of shift registers and a plurality of memory matrices forming a memory bank in which the matrices are spatially separated by the shift register. An integrated printhead may comprise a number of memory banks each comprising a plurality of memory matrices and a number of shift registers in which each shift register spatially separates a number of the matrices.

Abstract: A nozzle firing cell may comprise a firing transistor and a pre-charge transistor having a source and drain coupled between a pre-charge line and a gate of the firing transistor wherein the pre-charge line is routed over the gate of the pre-charge transistor. A fluid ejection device may comprise a circuit comprising a nozzle firing cell, the nozzle firing cell comprising a firing transistor and a pre-charge transistor having a source and drain coupled between a pre-charge Sine and a gate of the firing transistor in which the pre-charge line is routed over the gate of the pre-charge transistor. A circuit may comprise a number of firing transistors and a number of pre-charge transistors each having a source and drain coupled between a pre-charge line and a gate of one of the firing transistors in which the pre-charge line is routed over each of the gates of the pre-charge transistors.

Abstract: In an example implementation, a grounding structure includes a perimeter ground line around the perimeter of a printhead die, and having north, south, east, and west segments. The structure includes an inter-slot ground line extending from the north segment to the south segment between two fluid slots, and an alternative ground line extending from the east segment to the west segment and intersecting the inter-slot ground line in a connection area near ends of the fluid slots.

Abstract: A split memory bank may comprise a number of memory matrices forming a memory bank and a shift register in which the shift register physically separates the matrices. An integrated circuit may comprise a number of shift registers and a plurality of memory matrices forming a memory bank in which the matrices are spatially separated by the shift register. An integrated printhead may comprise a number of memory banks each comprising a plurality of memory matrices and a number of shift registers in which each shift register spatially separates a number of the matrices.

Abstract: In an example implementation, a grounding structure includes a perimeter ground line around the perimeter of a printhead die, and having north, south, east, and west segments. The structure includes an inter-slot ground line extending from the north segment to the south segment between two fluid slots, and an alternative ground line extending from the east segment to the west segment and intersecting the inter-slot ground line in a connection area near ends of the fluid slots.

Abstract: In an example implementation, a grounding structure includes a perimeter ground line around the perimeter of a printhead die, and having north, south, east, and west segments. The structure includes an inter-slot ground line extending from the north segment to the south segment between two fluid slots, and an alternative ground line extending from the east segment to the west segment and intersecting the inter-slot ground line in a connection area near ends of the fluid slots.

Abstract: A nozzle firing cell may comprise a firing transistor and a pre-charge transistor having a source and drain coupled between a pre-charge line and a gate of the firing transistor wherein the pre-charge line is routed over the gate of the pre-charge transistor. A fluid ejection device may comprise a circuit comprising a nozzle firing ceil, the nozzle firing cell comprising a firing transistor and a pre-charge transistor having a source and drain coupled between a pre-charge Sine and a gate of the firing transistor in which the pre-charge line is routed over the gate of the pre-charge transistor. A circuit may comprise a number of firing transistors and a number of pre-charge transistors each having a source and drain coupled between a pre-charge line and a gate of one of the firing transistors in which the pre-charge line is routed over each of the gates of the pre-charge transistors.

Abstract: A split memory bank may comprise a number of memory matrices forming a memory bank and a shift register in which the shift register physically separates the matrices. An integrated circuit may comprise a number of shift registers and a plurality of memory matrices forming a memory bank in which the matrices are spatially separated by the shift register. An integrated printhead may comprise a number of memory banks each comprising a plurality of memory matrices and a number of shift registers in which each shift register spatially separates a number of the matrices.