Abstract: Implementations are disclosed for a centralized peripheral access controller (PAC) that is configured to protect one or more peripheral components in a system. In some implementations, the PAC stores data that can be set or cleared by software. The data corresponds to an output signal of the PAC that is routed to a corresponding peripheral component. When the data indicates that the peripheral is “unlocked” the PAC will allow write transfers to registers in the peripheral component. When the data indicates that the peripheral component is “locked” the PAC will refuse write transfers to registers in the peripheral component and terminate with an error.

Abstract: Implementations are disclosed for a centralized peripheral access controller (PAC) that is configured to protect one or more peripheral components in a system. In some implementations, the PAC stores data that can be set or cleared by software. The data corresponds to an output signal of the PAC that is routed to a corresponding peripheral component. When the data indicates that the peripheral is “unlocked” the PAC will allow write transfers to registers in the peripheral component. When the data indicates that the peripheral component is “locked” the PAC will refuse write transfers to registers in the peripheral component and terminate with an error.

Abstract: A flexible-width peripheral register mapping is disclosed for accessing peripheral registers on a peripheral bus.

Abstract: Implementations are disclosed for a centralized peripheral access controller (PAC) that is configured to protect one or more peripheral components in a system. In some implementations, the PAC stores data that can be set or cleared by software. The data corresponds to an output signal of the PAC that is routed to a corresponding peripheral component. When the data indicates that the peripheral is “unlocked” the PAC will allow write transfers to registers in the peripheral component. When the data indicates that the peripheral component is “locked” the PAC will refuse write transfers to registers in the peripheral component and terminate with an error.

Abstract: A device comprises a central processing unit (CPU), a display controller configured for controlling a digital display and a memory configured for storing data corresponding to the digital display. The device includes a direct memory access (DMA) controller configured for autonomously transferring the data from the memory directly to the display controller without CPU intervention.

Abstract: A flexible-width peripheral register mapping is disclosed for accessing peripheral registers on a peripheral bus.

Abstract: Implementations are disclosed for a centralized peripheral access controller (PAC) that is configured to protect one or more peripheral components in a system. In some implementations, the PAC stores data that can be set or cleared by software. The data corresponds to an output signal of the PAC that is routed to a corresponding peripheral component. When the data indicates that the peripheral is “unlocked” the PAC will allow write transfers to registers in the peripheral component. When the data indicates that the peripheral component is “locked” the PAC will refuse write transfers to registers in the peripheral component and terminate with an error.

Abstract: A microcontroller for controlling a liquid crystal display (LCD) is mountable in any one of multiple package types. The microcontroller includes a LCD controller to generate logical mapping signals indicative of voltages to be applied to segment terminals of a LCD glass. A driver circuit drives the segment terminals selectively. A remapping unit receives the logical mapping signals from the LCD controller and maps the logical mapping signals, for each of the package types, to physical segment terminal drivers in the driver circuit based on a distribution of I/O terminals that are bonded for each package type when that package type is used with the LCD glass.

Abstract: A device comprises a central processing unit (CPU), a display controller configured for controlling a digital display and a memory configured for storing data corresponding to the digital display. The device includes a direct memory access (DMA) controller configured for autonomously transferring the data from the memory directly to the display controller without CPU intervention.

Abstract: A microcontroller for controlling a liquid crystal display (LCD) is mountable in any one of multiple package types. The microcontroller includes a LCD controller to generate logical mapping signals indicative of voltages to be applied to segment terminals of a LCD glass. A driver circuit drives the segment terminals selectively. A remapping unit receives the logical mapping signals from the LCD controller and maps the logical mapping signals, for each of the package types, to physical segment terminal drivers in the driver circuit based on a distribution of I/O terminals that are bonded for each package type when that package type is used with the LCD glass.

Abstract: A process for automatically detecting and configuring with the throughput of a network, in which a device: (a) goes into a listen mode; (b) obtains a triplet of successive transitions in a transmitted signal, the triplet delimiting first and second signal levels, one dominant and the other recessive; (c) measures the duration of each of the first and second levels; (d) as a function of the measured durations, obtains a new throughput configuration by determining values for parameters that define a bit length LBIT; (e) validates the new throughput configuration; (g) if at least one throughput adaptation condition is verified, goes into a normal mode, otherwise obtains a next transition of the signal, which delimits with the last previous transition a new level of the signal, then measures the duration of the new level and reiterates steps (d) to (g) taking account of the new signal level.

Abstract: A method for optimising writing by a master block into an interfacing device between the master block and a slave block. The method includes a step for transformation of a code into assembler language, done before the code in machine language is obtained and including the following steps: transformation of all static unit writes comprising more than one word from the assembler language code into one-word static unit writes; search for each set of N successive static one-word unit writes; replace at least one set of N successive static one-word unit writes by one static unit N-word write of, in the assembler language code, where N is an integer greater than or equal to 2.

Abstract: An interfacing device (23) of the type enabling one-way interfacing between a master unit (21) and a slave unit (22), includes: a memory plane managed according to a “first in, first out” mode, with write and read pointers, and making it possible to store words coming from the master unit, via an input bus (FIFODin); a bank of output registers capable of containing words read in the memory plane and providing an output signal (FIFODout) capable of being read by the slave unit; a mechanism configured to receive read requests (FIFORdRq=1) coming from the slave unit and write requests (FIFOWr=1) coming from the master unit, each read request requiring the reading of a word group.

Abstract: A process for automatically detecting throughput of a network by a device. The network transmits a signal on which messages are carried that include bits of length LBIT and of a dominant or recessive type.