Abstract: The symbols of a first code are represented by sign and magnitude bits in a manner analogous to the sign and magnitude bits representing the symbols of a second code. A memory stores digital samples partially representing coding pulses, and each pair of sign and magnitude bits is used to control a common shaping filter. The shaping filter uses the samples stored in the memory to generate a sampled digital signal representative of the analog signal transmitted over the telephone line.

Abstract: The present invention relates to a master transceiver circuit meant to be coupled by a telephone line to a slave transceiver circuit, the master circuit including a digital phase-locked loop for reconstructing a clock from an incoming bit flow, the phase difference between the reconstructed clock and an internal clock corresponding to the content of a phase counter of the phase-locked loop. The circuit includes a bit counter clocked by the internal clock, initialized upon transmission of a predetermined signal, and stopped upon detection of the return of the predetermined signal transmitted back by the slave transceiver circuit; and means for calculating the delay introduced by the telephone line based on the contents of the phase and bit counters.

Abstract: A full duplex transmission circuit for a signal having alternating synchronization words with data words. The circuit comprising a phase-locked loop including a frequency synchronizer adapted to provide an emission clock signal. A sampling signal having its phase locked on the shift between an emitted signal and a received signal is generated using a clock signal provided by the phase-locked loop. The circuit includes circuitry for imparting to the frequency synchronizer a frequency multiplier function to reduce a duration of phase skips of the sampling signal.

Abstract: A programmable frequency sine wave signal generator, including a generator for generating square-wave signals having a programmable frequency; a counter for counting the periods of the square-wave signals; circuits for providing successive discrete sine wave values from successive states of the counter; and a low-pass filter receiving the successive discrete sine wave values and providing the sine wave. The low-pass filter is a switched-capacitor filter with a switching mode that is controlled by a signal having a frequency proportional to the frequency of the square-wave signal. Correct selection of the values of the filter capacitors allows the cut-off frequency of the filter to be continuously substantially the same as the frequency of the sine wave.

Abstract: A device for regulating the common mode output voltage of a balanced amplifier having two differential outputs, including a differential stage providing a correction signal of the common mode voltage corresponding to the difference between a reference voltage and the average differential output voltage of the amplifier, and further including a current generator that sets a polarization current of the differential stage, the current generator being controlled by the output current of the balanced amplifier.

Abstract: A circuit pulls up an integrated circuit input capable of receiving a low voltage, receiving a high voltage, or floating. The circuit includes a first MOS transistor connected between the input and the high voltage; a serial connection between the high and low voltages of a second, third, and fourth MOS transistor; a connection between the gates of the first and second transistors and the junction of the third and fourth transistors; and a connection between the input and the gates of the third and fourth transistors.

Abstract: In a CMOS amplifier having a differential input and differential output, the input stage includes two legs, each of which includes an input transistor. A common mode negative feedback stage includes a load connected to the high supply voltage, a first transistor connected between the load and a common terminal of the input transistors. The first transistor is biased to the desired common mode voltage. A second transistor is connected between the load and the low supply voltage, and has a gate connected to a voltage corresponding to the mean voltage of the output stage. An additional transistor is disposed in parallel with each input transistor. Each additional transistor has its gate connected to the desired common mode voltage.

Abstract: In a CMOS amplifier having a differential input and differential output, the input stage includes two legs, each of which includes an input transistor. A common mode negative feedback stage includes a load connected to the high supply voltage, a first transistor connected between the load and a common terminal of the input transistors. The first transistor is biased to the desired common mode voltage. A second transistor is connected between the load and the low supply voltage, and has a gate connected to a voltage corresponding to the means voltage of the output stage. An additional transistor is disposed in parallel with each input transistor. Each additional transistor has its gate connected to the desired common mode voltage.

Abstract: A generator capable of forming an analog signal having a waveform determined from a sequence of digital control words applied at a high frequency, each word representing an increment of the analog signal to be produced at the output. For this type of generator, the accuracy of the increment value is an essential parameter. If several increments having a different value are generated as a function of the control word, their ratio has to be very accurate. The diclosed circuit is of the switched-capacitor type; it comprises several input capacitors (C1, C2, C3) that are theoretically identical. In order to take into account the dispersion due to manufacturing, a procedure for choosing the best input capacitor is previously established for obtaining a precise ratio between the increments (+V, +3V, -V, -3V) that can be supplied at the output. This procedure consists in comparing capacitors by pairs to sequence them and select the median capacitor.

Abstract: A circuit is disclosed for the transmission of digital signals on a bifilary line, especially a telephone line. The circuit disclosed is a so-called S interface circuit which has to produce digital signals within certain set limits. The proposed circuit uses four differential amplifiers, each controlling an output transistor (N-channel MOS transistors and P-channel MOS transistors). The amplifiers receive feedback to maintain the overvoltages within acceptable limits. The invention applies especially to the setting up of integrated service digital telephone networks.

Abstract: The invention provides a high-speed binary multiplier.The binary digits x.sub.i of the multiplicand X and y.sub.j of the multiplier Y (in two complement form) are converted by respective coders into coefficients a.sub.i and b.sub.j such thatX=a.sub.m-1 2.sup.m-1 + . . . a.sub.1 2.sup.1 +a.sub.oY=b.sub.n-1 2.sup.n-1 + . . . b.sub.1 2.sup.1 +b.sub.owhere a.sub.i and b.sub.j can only assume three values 0,1 or -1 and where two consecutive coefficients a.sub.i and a.sub.i-1 and b.sub.j or b.sub.j-1 cannot both be non zero. a.sub.i and b.sub.j are each represented by a pair of binary logic signals (r.sub.i,u.sub.i) or (s.sub.j,v.sub.j). The signals (s.sub.j,v.sub.j) serve for controlling a routing circuit which further receives as signals to be routed the signals (r.sub.i,u.sub.i) for directing these signals, depending on the values of coefficients b.sub.j, to the appropriate inputs of an adder stage operating without carry-over propagation. The outputs of this adder are reconverted into binary form by a decoder.