Abstract: A microcontroller includes I/O pins whose respective functions are configurable by an I/O controller in accordance with user-programmable input. The availability of such configurable I/O pins is extended to low-power or power savings modes of operation during which the I/O controller is powered off or deactivated.

Abstract: A microcontroller system includes a higher power reference voltage circuit and a lower power reference voltage circuit configured to draw less power than the higher power reference voltage circuit when enabled. The system includes a power state logic controller configured to enable the lower power reference voltage circuit to provide a first regulated voltage during a power saving mode, and, on exiting the power saving mode, enable the higher power reference voltage circuit to provide a second regulated voltage.

Abstract: A microcontroller system includes a main voltage regulator and a low power voltage regulator having a static current consumption less than the static current consumption of the main voltage regulator. A power state controller enables the low power voltage regulator during a power saving mode. On exiting the power saving mode, the power state controller enables the main voltage regulator and disables the low power voltage regulator after determining that the main voltage regulator is ready. The switching circuitry can be asynchronous.

Abstract: Access of multiple data processing circuits to a common memory having several banks is managed, the memory being connected to one or several circuits for processing ordinary data and to a circuit for processing priority data. A method of managing access includes producing an access demand of a circuit for processing ordinary data to a bank of the memory, starting the realization of the demanded access, subsequently producing an access demand of the circuit for processing priority data to another bank of the memory, preparing, during the realization of the access demanded by the ordinary data processing circuits, the other bank of the memory, and interrupting the access in the course of realization as soon as said preparation is completed.

Abstract: Method of managing access of a plurality of data processing circuits (4, 7) to a common memory (1) comprising several banks (A-D), the memory being connected to one or several circuits (7) for processing ordinary data and to a circuit (4) for processing priority data, the method comprising the steps of:—producing an access demand of the or one of the circuits for processing ordinary data to a bank of the memory;—starting the realization of the demanded access;—subsequently producing an access demand of the circuit for processing priority data to another bank of the memory;—preparing (PRE, ACT), during the realization of the access demanded by the or one of the ordinary data processing circuits, said other bank of the memory;—interrupting the access in the course of realization as soon as said preparation is completed.