Abstract: A portable electronic device may include a housing, a display at least partially within the housing, a transparent cover over the display, and a battery at least partially within the housing. The battery may include a battery cell, a pouch encasing the battery cell, and a gas release relief system including a gas-permeable membrane configured to prevent liquid from escaping the pouch and a valve configured to selectively release gas from the pouch. The device may also include a processing system configured to, in a first mode of operation, cause the valve to open to allow gas to be released from the pouch, and, in a second mode of operation, cause the valve to close.

Abstract: A portable electronic device may include a housing, a display at least partially within the housing, a transparent cover over the display, and a battery at least partially within the housing. The battery may include a battery cell, a pouch encasing the battery cell, and a gas release relief system including a gas-permeable membrane configured to prevent liquid from escaping the pouch and a valve configured to selectively release gas from the pouch. The device may also include a processing system configured to, in a first mode of operation, cause the valve to open to allow gas to be released from the pouch, and, in a second mode of operation, cause the valve to close.

Abstract: A circuit board comprising a contacting arrangement, including three metal contacting regions, which are connected with one or more data links of the circuit board and in the case of contact with a communication interface of a test system enable a data exchange with a data memory of a circuit board.

Abstract: A test system for checking electrical connections, especially solder connections, between electronic components with a circuit board to be checked, characterized in that the test system includes a communication interface with at least three electrically-conductive contact tips, which by contact with a contacting arrangement on the circuit board having a number of contacting locations enable a data exchange with a data memory and/or a communication module of a circuit board, wherein the data exchange occurs according to a communication protocol.

Abstract: A test system for testing electric connections, in particular soldered connections, between electronic components and a printed circuit board to be tested, characterized in that the test system includes a subassembly, which is movably mounted in a housing of the test system, and a current and/or voltage source for energizing the circuit board to be tested, the current and/or voltage source being arranged in the housing of the test system in such a way as to be movable in at least two directions in space.

Abstract: A test system for testing electrical connections, especially soldered connections, between electronic components and a circuit board to be tested, characterized in that the test system has a communication interface, which by contacting the circuit board enables a data exchange with a data memory or a communication module of the circuit board to be tested, wherein the communication interface is arranged within a housing of the test system freely movably in at least two spatial directions, preferably three spatial directions.

Abstract: Disclosed is a test system for testing electric connections, in particular soldered connections, between electronic components and a printed circuit board to be tested, characterized in that the test system includes a subassembly, which is movably mounted in a housing of the test system, and a current and/or voltage source for energizing the circuit board to be tested, the current and/or voltage source being arranged in the housing of the test system in such a way as to be movable in at least two directions in space.

Abstract: A test system for testing electrical connections, especially soldered connections, between electronic components and a circuit board to be tested, characterized in that the test system has a communication interface, which by contacting the circuit board enables a data exchange with a data memory or a communication module of the circuit board to be tested, wherein the communication interface is arranged within a housing of the test system freely movably in at least two spatial directions, preferably three spatial directions.

Abstract: A test system for checking electrical connections, especially solder connections, between electronic components with a circuit board to be checked, characterized in that the test system includes a communication interface with at least three electrically-conductive contact tips, which by contact with a contacting arrangement on the circuit board having a number of contacting locations enable a data exchange with a data memory and/or a communication module of a circuit board, wherein the data exchange occurs according to a communication protocol.

Abstract: A test system (1) for testing electric connections, in particular soldered connections, between electronic components and a printed circuit board (6) to be tested, characterized in that the test system (1) includes a subassembly, which is movably mounted in a housing (1a) of the test system, and a current and/or voltage source (14) for energizing the circuit board (6) to be tested, the current and/or voltage source (14) being arranged in the housing (1a) of the test system (1) in such a way as to be movable in at least two directions in space.

Abstract: Disclosed is a test system for testing electric connections, in particular soldered connections, between electronic components and a printed circuit board to be tested, characterized in that the test system includes a subassembly, which is movably mounted in a housing of the test system, and a current and/or voltage source for energizing the circuit board to be tested, the current and/or voltage source being arranged in the housing of the test system in such a way as to be movable in at least two directions in space.

Abstract: A circuit board comprising a contacting arrangement, including three metal contacting regions, which are connected with one or more data links of the circuit board and in the case of contact with a communication interface of a test system enable a data exchange with a data memory of a circuit board.

Abstract: A modular test controller with a built-in self-test (BIST) circuit for testing an embedded DRAM (eDRAM) circuit is provided. The test controller includes a built-in self-test (BIST) core for performing tests, the BIST core including proven testing algorithms; a selectable tester interface for interfacing the BIST core with an external tester; and a selectable eDRAM interface for interfacing the BIST core with an eDRAM, the eDRAM including a plurality of memory cells for storing data. The present invention allows semiconductor device designers to keep to one testflow and reuse a proven BIST core over multiple ASIC (Application Specific Integrated Circuits) products/generations.

Abstract: A circuit and method for testing an eDRAM through a test controller with direct access (DA) mode logic is provided. The circuit and method of the present invention allows the testing of eDRAMs with a conventional memory tester. The present invention provides a semiconductor device including an embedded dynamic random access memory (eDRAM) for storing data, the eDram including a plurality of memory cells, and a test controller for testing the plurality of memory cells to determine if the cells are defective, the test controller including built-in self-test (BIST) logic circuitry for performing tests and for interfacing to a logic tester, and direct access mode logic circuitry for interfacing the eDRAM with an external memory tester. The test controller further comprises a multiplexer for multiplexing data, commands, and addresses from the BIST logic circuitry and the direct access mode logic circuitry to the eDRAM.

Abstract: External test equipment is used to simulate an internal BIST test, thus enabling the capture or generation of detailed test results. By simulating the BIST test sequence in real time during the test, the external tester may monitor an output from the BIST and determine the exact location of failures when they occur. The external tester may generate a bit fail map indicating whether each memory location passed or failed the BIST test.

Abstract: A memory apparatus is configured by obtaining test information for each of group of memory locations within the memory apparatus, compressing the test information to produced compressed test information and, based on the compressed test information, replacing a group of redundant memory circuits respectively associated with the group of memory locations.

Abstract: External test equipment is used to simulate an internal BIST test, thus enabling the capture or generation of detailed test results. By simulating the BIST test sequence in real time during the test, the external tester may monitor an output from the BIST and determine the exact location of failures when they occur. The external tester may generate a bit fail map indicating whether each memory location passed or failed the BIST test.

Abstract: A modular test controller with a built-in self-test (BIST) circuit for testing an embedded DRAM (eDRAM) circuit is provided. The test controller includes a built-in self-test (BIST) core for performing tests, the BIST core including proven testing algorithms; a selectable tester interface for interfacing the BIST core with an external tester; and a selectable eDRAM interface for interfacing the BIST core with an eDRAM, the eDRAM including a plurality of memory cells for storing data. The present invention allows semiconductor device designers to keep to one testflow and reuse a proven BIST core over multiple ASIC (Application Specific Integrated Circuits) products/generations.

Abstract: A circuit and method for testing an eDRAM through a test controller with direct access (DA) mode logic is provided. The circuit and method of the present invention allows the testing of eDRAMs with a conventional memory tester. The present invention provides a semiconductor device including an embedded dynamic random access memory (eDRAM) for storing data, the eDRAM including a plurality of memory cells; and a test controller for testing the plurality of memory cells to determine if the cells are defective, the test controller including built-in self-test (BIST) logic circuitry for performing tests and for interfacing to a logic tester; and direct access mode logic circuitry for interfacing the eDRAM with an external memory tester. The test controller further comprises a multiplexer for multiplexing data, commands, and addresses from the BIST logic circuitry and the direct access mode logic circuitry to the eDRAM.

Abstract: A precharge command can be issued to a single bank or a precharge-all command can be issued to all banks of an integrated circuit memory device (e.g., DRAM circuit) at any time during normal operation of the device. Internal circuits are provided to decode the respective commands and send them to the different independent memory banks of the integrated circuit memory device. A local precharge control unit (or circuit) is present inside each of the memory banks that can receive and process the decoded precharge commands. If certain specified timing conditions are met, the local precharge control unit can issue and store a precharge request for a specific bank. The precharge request can be held back until all timing requirements are fulfilled. The precharge request can then be automatically executed.