Abstract: A signal filter system which uses two groups of switches to couple tap current cells with integrating cells. The first group of switches couples tap current cells with at least one shared connection or bus while the other group of switches couples the shared connection or bus with the integrating cells. Multiple shared connections can be used and the tap current cells can be divided into groups with each group sharing at least one shared connection that is dedicated to that group. The system also allows for more than one tap current cell to simultaneously be coupled to a single integrating cell.

Abstract: A delta sigma modulator which uses at least one quantizer having a dead zone. The dead zone quantizer outputs a zero when its input is within the dead zone range. It outputs a predetermined value if the input is above the dead zone range. If the input is below the dead zone range, the quantizer outputs another predetermined value. Ideally, the quantizer dead zone thresholds are complimentary in that the upper threshold for an input is the positive value of the lower threshold. Also, to save on accumulator bits, the delta sigma modulator selects a predetermined number of most significant bits at different stages.

Abstract: PLL frequency synthesizers and their calibration techniques are described. The PLL frequency synthesizers are used to generate digital modulation of a carrier signal. A digital frequency divider in the feedback path of the loop has its division ratio controlled by a digital &Dgr;-&Sgr; modulator. The modulation of the carrier is achieved by applying a modulation signal to the input of the &Dgr;-&Sgr; modulator and to the input of the voltage-controlled oscillator of the PLL. The high frequency path and low frequency path of the modulation signal must be adjusted with respect to one another in order to obtain a good modulation. As the low frequency path can be accurately set, the calibration is performed only on the high frequency path. Digital calibration techniques for the high frequency path are described.

Abstract: A method and an apparatus relating to a PLL circuit for frequency synthesizer applications. By using a composite PFD large and small phase variations between a reference signal and the divider output are compensated for. The composite phase frequency detector (PFD) has both a digital phase frequency detector (digital PFD) and an analog phase detector (analog PD) with the digital PFD compensating for large phase differences and the analog PD compensating for smaller phase differences. The PLL automatically chooses between these two components in the composite PFD by controlling the pulse width of the divider output. This is accomplished by synchronizing the dead zone of the digital PFD with the active pulse width of the divider output and by similarly synchronizing the phase detector window of the analog PD to be within both the dead zone of the digital PFD and the active pulse width of the divider output.

Abstract: A delta sigma modulator which uses at least one quantizer having a dead zone. The dead zone quantizer outputs a zero when its input is within the dead zone range. It outputs a predetermined value if the input is above the dead zone range. If the input is below the dead zone range, the quantizer outputs another predetermined value. Ideally, the quantizer dead zone thresholds are complimentary in that the upper threshold for an input is the positive value of the lower threshold. Also, to save on accumulator bits, the delta sigma modulator selects a predetermined number of most significant bits at different stages.

Abstract: A delta-sigma modulator having a dead-zone quantizer and an error shaping digital filter clocked by a signal which is periodic at the frequency of the reference. A dead-zone quantizer provides quantization of a high resolution digital word to a low resolution digital word with three or a higher odd number of possible output levels and with an output of zero for an input near the center of the normal input range. The delta-sigma modulator is used in a fractional-N divider. The fractional-N divider is used in a fractional-N frequency synthesizer.

Abstract: A fractional-N frequency synthesizer comprises a voltage-controlled oscillator (107) for generating an output signal (F.sub.o) in response to a control voltage derived by a digital-to-analog converter (105) from a digital error signal (e). The error signal is derived by a differencing device (103) which subtracts a digital signal (D.sub.o) representing the actuated frequency of the output signal from an input signal (F.sub.d) having the desired frequency for the output signal. The digital signal representing the output signal frequency is derived by a frequency discrimination device (101) which determines the instant frequency of the analog output signal and provides a corresponding digital representation with zero static frequency error. In preferred embodiments, the frequency discrimination device is a delta-sigma frequency synthesizer in combination with a decimator (102). This frequency synthesizer configuration avoids deficiencies due to non-linearity and noise sensitivity of analog phase detectors.

Abstract: An indirect frequency synthesizer suitable for use in a cellular radio system has finer resolution and reduced spurious frequencies and/or phase noise, which facilitates a large number of channels in a given bandwidth. The synthesizer comprises a phase detector responsive to a reference signal and a phase control signal for generating a control signal that varies in dependence upon the phase difference between the reference signal and the phase control signal. A voltage controlled oscillator responsive to the control signal generates an output signal whose frequency varies in dependence upon the control signal. A variable modulus divider divides the output signal to provide the phase control signal. The variable modulus divider varies its division ratio in dependence upon a ratio control signal derived by a second or higher order sigma-delta modulator in response to a frequency control signal .delta..phi. and to the phase control signal.