Patents by Inventor Thomas A. Gregg
Thomas A. Gregg has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9571572Abstract: Embodiments relate to two general purpose computers connected in a peer-to-peer mode by connecting a cable (or wireless connection) between universal ports (e.g., PCIe ports) on each computer. A timing protocol utility runs on each computer to time schedule operations performed by its respective computer. Because the system clocks on each peer computer operate independently (asynchronously), they may vary somewhat from each other. To support time synchronized peer-to-peer operations, paired clock value (one for each peer computer) are generated continually and independently by each peer system. Each peer system periodically supplies the paired clock values to its associated timing protocol utility, which uses the paired clock values to time synchronize peer-to-peer computer operations. The timing protocol utilities may also exchange the paired clock values with each other for integrity checking and other operations.Type: GrantFiled: May 1, 2014Date of Patent: February 14, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Richard K. Errickson, Thomas A. Gregg, Kulwant M. Pandey
-
Patent number: 9547613Abstract: Embodiments include a method and computer program product for dynamic universal port mode assignment for a general purpose computer system. A host bridge with a mixed mode request router routes requests received over a universal peripheral component interconnect express (PCIe) port from PCIe adapters utilizing different operating modes. An aspect includes a general purpose host computer with one or more PCIe universal ports allowing the computer to connect to a wide range of external peripheral devices, such as a local area networks, storage area networks, printers, scanners, graphics controllers, game systems, and so forth. PCIe is a modern universal port protocol for parallel ports that allows peripherals utilizing different operating modes to connect to a standard PCIe parallel port. The mixed mode request router supports converged PCIe adapters, which support multiple functions utilizing different PCIe modes converged onto the same mixed mode adapter.Type: GrantFiled: September 30, 2014Date of Patent: January 17, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David F. Craddock, Thomas A. Gregg, Eric N. Lais
-
Patent number: 9542243Abstract: Embodiments are directed to systems and methodologies for allowing a computer program code to efficiently respond to and process events. For events having a multiple stage completion sequence, and wherein several of the events occur within relatively close time proximity to each other, portions of the multiple stages may be coalesced without adding latency, thereby maintaining responsiveness of the computer program. The disclosed coalescing systems and methodologies include state machines and counters that in effect “replace” certain stages of the event sequence when the frequency of events increases.Type: GrantFiled: March 14, 2014Date of Patent: January 10, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Thomas A. Gregg, Kulwant M. Pandey
-
Publication number: 20160352819Abstract: Embodiments relate to two general purpose computers connected in a peer-to-peer mode by connecting a cable (or wireless connection) between universal ports (e.g., PCIe ports) on each computer. A timing protocol utility runs on each computer to time schedule operations performed by its respective computer. Because the system clocks on each peer computer operate independently (asynchronously), they may vary somewhat from each other. To support time synchronized peer-to-peer operations, paired clock value (one for each peer computer) are generated continually and independently by each peer system. Each peer system periodically supplies the paired clock values to its associated timing protocol utility, which uses the paired clock values to time synchronize peer-to-peer computer operations. The timing protocol utilities may also exchange the paired clock values with each other for integrity checking and other operations.Type: ApplicationFiled: August 23, 2016Publication date: December 1, 2016Inventors: Richard K. Errickson, Thomas A. Gregg, Kulwant M. Pandey
-
Patent number: 9483436Abstract: Embodiments relate to an enhancement of a function measurement block. An aspect includes obtaining common statistics from a function table. An aspect includes obtaining adapter-specific statistics from an adapter. An aspect includes providing the common statistics and the adapter-specific statistics in the function measurement block. An aspect includes providing adapter-specific counters in the function measurement block.Type: GrantFiled: September 30, 2014Date of Patent: November 1, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David Craddock, Beth A. Glendening, Thomas A. Gregg, Dan F. Greiner
-
Patent number: 9465681Abstract: Embodiments are directed to systems and methodologies for allowing a computer program code to efficiently respond to and process events. For events having a multiple stage completion sequence, and wherein several of the events occur within relatively close time proximity to each other, portions of the multiple stages may be coalesced without adding latency, thereby maintaining responsiveness of the computer program. The disclosed coalescing systems and methodologies include state machines and counters that in effect “replace” certain stages of the event sequence when the frequency of events increases.Type: GrantFiled: March 17, 2016Date of Patent: October 11, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Thomas A. Gregg, Kulwant M. Pandey
-
Patent number: 9465768Abstract: Embodiments relate to an enhancement of a function measurement block. An aspect includes obtaining common statistics from a function table. An aspect includes obtaining adapter-specific statistics from an adapter. An aspect includes providing the common statistics and the adapter-specific statistics in the function measurement block. An aspect includes providing adapter-specific counters in the function measurement block.Type: GrantFiled: March 14, 2014Date of Patent: October 11, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David Craddock, Beth A. Glendening, Thomas A. Gregg, Dan F. Greiner
-
Publication number: 20160292088Abstract: A dynamic storage key assignment is provided. An aspect includes receiving, by a host bridge, a request. An aspect includes determining, by the host bridge, that a dynamic storage key assignment is supported and enabled in association with a memory address space referenced by the request based on a requester identifier or a portion of a peripheral component interconnect address associated with the request. An aspect includes, based on determining that the dynamic storage key assignment is supported and enabled, accessing, by the host bridge, a page included in the memory address space based on a storage key included in the request matching a storage key associated with the page being accessed or an entry in a listing of permitted storage keys for the memory address space.Type: ApplicationFiled: June 22, 2016Publication date: October 6, 2016Inventors: David F. Craddock, Thomas A. Gregg
-
Publication number: 20160292082Abstract: A method of enhancing a refresh PCI translation (RPCIT) operation to refresh a translation lookaside buffer (TLB) includes determining, by a computer processor, a request to perform at least one RPCIT instruction for purging at least one translation from the TLB. The method further includes purging, by the computer processor, the at least one translation from the TLB in response to executing the at least one RPCIT instruction. The computer processor selectively performs a synchronization operation prior to completing the at least one RPCIT instruction.Type: ApplicationFiled: June 22, 2016Publication date: October 6, 2016Inventors: David F. Craddock, Thomas A. Gregg, Dan F. Greiner, Damian L. Osisek
-
Patent number: 9456032Abstract: Embodiments relate to two general purpose computers connected in a peer-to-peer mode by connecting a cable (or wireless connection) between universal ports (e.g., PCIe ports) on each computer. A timing protocol utility runs on each computer to time schedule operations performed by its respective computer. Because the system clocks on each peer computer operate independently (asynchronously), they may vary somewhat from each other. To support time synchronized peer-to-peer operations, paired clock value (one for each peer computer) are generated continually and independently by each peer system. Each peer system periodically supplies the paired clock values to its associated timing protocol utility, which uses the paired clock values to time synchronize peer-to-peer computer operations. The timing protocol utilities may also exchange the paired clock values with each other for integrity checking and other operations.Type: GrantFiled: March 14, 2016Date of Patent: September 27, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Richard K. Errickson, Thomas A. Gregg, Kulwant M. Pandey
-
Patent number: 9384086Abstract: Error checking in a computing environment at an input/output (I/O) level is facilitated by associating a cyclic redundancy check (CRC) control element (CCE) with an input/output (I/O) operation based on a command to perform the I/O operation of the computing environment. The CRC control element is used in accumulating during performance of the I/O operation an accumulated CRC value for the I/O operation to facilitate error checking of the I/O operation. By way of example, the associating and the accumulating of the accumulated CRC value may be performed within an I/O hub of the computing environment, and where data of the I/O operation is transferred in data fragments, the CRC control element is updated for each data fragment during the accumulating of the CRC context for the I/O operation.Type: GrantFiled: November 30, 2015Date of Patent: July 5, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David Craddock, John R. Flanagan, Thomas A. Gregg
-
Patent number: 9383931Abstract: An instruction is provided to establish various operational parameters for an adapter. These parameters include adapter interruption parameters, input/output address translation parameters, resetting error indications, setting measurement parameters, and setting an interception control, as examples. The instruction specifies a function information block, which is a program representation of a device table entry used by the adapter, to be used in certain situations in establishing the parameters. A store instruction is also provided that stores the current contents of the function information block.Type: GrantFiled: May 2, 2012Date of Patent: July 5, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David Craddock, Mark S. Farrell, Beth A. Glendening, Thomas A. Gregg, Dan F. Greiner, Gustav E. Sittmann, III, Peter K. Szwed
-
Patent number: 9384158Abstract: Embodiments include a system for dynamic universal port mode assignment for a general purpose computer system. A host bridge with a mixed mode request router receives requests over a universal peripheral component interconnect express (PCIe) port from PCIe adapters utilizing different operating modes. An aspect includes a general purpose host computer with one or more PCIe universal ports allowing the computer to connect to a wide range of external peripheral devices, such as a local area networks, storage area networks, printers, scanners, graphics controllers, game systems, and so forth. PCIe is a modern universal port protocol for parallel ports that allows peripherals utilizing different operating modes to connect to a standard PCIe parallel port. The mixed mode request router supports converged PCIe adapters, which support multiple functions utilizing different PCIe modes converged onto the same mixed mode adapter.Type: GrantFiled: March 14, 2014Date of Patent: July 5, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David F. Craddock, Thomas A. Gregg, Eric N. Lais
-
Publication number: 20160188389Abstract: Embodiments are directed to systems and methodologies for allowing a computer program code to efficiently respond to and process events. For events having a multiple stage completion sequence, and wherein several of the events occur within relatively close time proximity to each other, portions of the multiple stages may be coalesced without adding latency, thereby maintaining responsiveness of the computer program. The disclosed coalescing systems and methodologies include state machines and counters that in effect “replace” certain stages of the event sequence when the frequency of events increases.Type: ApplicationFiled: March 17, 2016Publication date: June 30, 2016Inventors: Thomas A. Gregg, Kulwant M. Pandey
-
Publication number: 20160182621Abstract: Embodiments relate to two general purpose computers connected in a peer-to-peer mode by connecting a cable (or wireless connection) between universal ports (e.g., PCIe ports) on each computer. A timing protocol utility runs on each computer to time schedule operations performed by its respective computer. Because the system clocks on each peer computer operate independently (asynchronously), they may vary somewhat from each other. To support time synchronized peer-to-peer operations, paired clock value (one for each peer computer) are generated continually and independently by each peer system. Each peer system periodically supplies the paired clock values to its associated timing protocol utility, which uses the paired clock values to time synchronize peer-to-peer computer operations. The timing protocol utilities may also exchange the paired clock values with each other for integrity checking and other operations.Type: ApplicationFiled: March 14, 2016Publication date: June 23, 2016Inventors: Richard K. Errickson, Thomas A. Gregg, Kulwant M. Pandey
-
Publication number: 20160179720Abstract: Embodiments relate to an implementation of a device table in system memory to which a peripheral component interface (PCI) adapter is coupled via a host bridge. An aspect includes an access of the device table in the system memory by a switch coupled to the host bridge, management of a device table entry (DTE) cache in the host bridge for coherency for DTE configuration changes and maintenance of a usage count and an in-use count in the host bridge for each cached DTE.Type: ApplicationFiled: March 11, 2016Publication date: June 23, 2016Inventors: David F. Craddock, Thomas A. Gregg, Eric N. Lais
-
Publication number: 20160173380Abstract: Embodiments are directed to a computer system for managing data transfer. The computer system includes a memory, a processor communicatively coupled to the memory, a send component and a receive component having a message queue and a controller. A link interface communicatively couples the send component to the receive component. The link interface includes a mainline channel and a sideband channel, and the computer system is configured to perform a method. The method includes transmitting mainline channel messages over the mainline channel from the send component to the receive component. The method further includes transmitting sideband channel messages over the sideband channel from the send component to the message queue of the receive component. The method further includes utilizing the controller to control a flow of the sideband channel messages to the message queue without relying on sending feedback to the send component about the flow.Type: ApplicationFiled: March 8, 2016Publication date: June 16, 2016Inventors: Richard K. Errickson, Thomas A. Gregg, Leonard W. Helmer, JR., Michael P. Lyons, Kulwant M. Pandey, Peter K. Szwed
-
Patent number: 9354967Abstract: Error-handling in a computing environment at an input/output (I/O) level is facilitated by associating a control element with an input/output (I/O) operation based on a command to perform the I/O operation between an adapter and memory. Based on detection of an error for the I/O operation, the control element is updated to indicate an error state, and completion of any uncompleted I/O request for the I/O operation is blocked, while other I/O requests for one or more other I/O operations are allowed to proceed between the adapter (or adapter function) and the memory. By way of example, the control element may be a cyclic redundancy check (CRC) control element used, for instance, by an I/O hub of the computing environment to accumulate during performance of the I/O operation an accumulated CRC value for the I/O operation to facilitate error checking of the operation.Type: GrantFiled: November 30, 2015Date of Patent: May 31, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David Craddock, John R. Flanagan, Thomas A. Gregg
-
Patent number: 9342352Abstract: An authorization mechanism allows a host executing a guest operating system to grant permission for the guest to directly access an adapter function's address spaces without host intervention. This access is via instructions implemented based on the architecture of the adapter function. The host also has the capability to intervene in the execution of the instruction, if desired.Type: GrantFiled: June 23, 2010Date of Patent: May 17, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David Craddock, Mark S. Farrell, Thomas A. Gregg, Dan F. Greiner, Damian L. Osisek, Gustav E. Sittmann, III
-
Patent number: 9321794Abstract: The invention includes processes for the synthesis of amphetamine, dexamphetamine, methamphetamine, derivatives of these, including their salts, and novel precursors and intermediates obtained thereby, by synthesizing aziridine phosphoramidate compounds in specified solvents at specified temperatures, and then converting to a novel aryl or aryl-alkyl phosphoramidate precursors using an organometallic compound such as a copper salt, where the novel aryl or aryl-alkyl phosphoramidate precursor is then easily converted to the target compounds using known reactions.Type: GrantFiled: July 9, 2014Date of Patent: April 26, 2016Assignee: CHEMAPOTHECA, LLCInventors: Harold Meckler, Brian Thomas Gregg, Jie Yang