Patents by Inventor Thomas A. Ziaja
Thomas A. Ziaja has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11961575Abstract: An integrated circuit (IC) includes first and scan latches that are enabled to load data during a first part of a clock period. A clocking circuit outputs latch clocks with one latch clock driven to an active state during a second part of the clock period dependent on a first address input. A set of storage elements have inputs coupled to the output of the first scan latch and are respectively coupled to a latch clock to load data during a time that their respective latch clock is in an active state. A selector circuit is coupled to outputs of the first set of storage elements and outputs a value from one output based on a second address input. The second scan latch then loads data from the selector's output during the first part of the input clock period.Type: GrantFiled: September 9, 2022Date of Patent: April 16, 2024Assignee: SambaNova Systems, Inc.Inventors: Thomas A. Ziaja, Uma Durairajan, Dinesh R. Amirtharaj
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Publication number: 20230005560Abstract: An integrated circuit (IC) includes first and scan latches that are enabled to load data during a first part of a clock period. A clocking circuit outputs latch clocks with one latch clock driven to an active state during a second part of the clock period dependent on a first address input. A set of storage elements have inputs coupled to the output of the first scan latch and are respectively coupled to a latch clock to load data during a time that their respective latch clock is in an active state. A selector circuit is coupled to outputs of the first set of storage elements and outputs a value from one output based on a second address input. The second scan latch then loads data from the selector's output during the first part of the input clock period.Type: ApplicationFiled: September 9, 2022Publication date: January 5, 2023Applicant: SambaNova Systems, Inc.Inventors: Thomas A. ZIAJA, Uma DURAIRAJAN, Dinesh R. AMIRTHARAJ
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Patent number: 11443823Abstract: Testability of memory on integrated circuits is improved by connecting storage elements like latches in memory to scan chains and configuring memory for scan dump. The use of latches and similar compact storage elements to form scannable memory can extend the testability of high-density memory circuits on complex integrated circuits operable at high clock speeds. A scannable memory architecture includes an input buffer with active low buffer latches, and an array of active high storage latches, operated in coordination to enable incorporation of the memory into scan chains for ATPG/TT and scan dump testing modes.Type: GrantFiled: September 7, 2021Date of Patent: September 13, 2022Assignee: SambaNova Systems, Inc.Inventors: Thomas A. Ziaja, Uma Durairajan, Dinesh R. Amirtharaj
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Patent number: 11443822Abstract: Testability of memory on integrated circuits is improved by connecting storage elements like latches in memory to scan chains and configuring memory for scan dump. The use of latches and similar compact storage elements to form scannable memory can extend the testability of high-density memory circuits on complex integrated circuits operable at high clock speeds. A scannable memory architecture includes an input buffer with active low buffer latches, and an array of active high storage latches, operated in coordination to enable incorporation of the memory into scan chains for ATPG/TT and scan dump testing modes.Type: GrantFiled: September 7, 2021Date of Patent: September 13, 2022Assignee: SambaNova Systems, Inc.Inventors: Thomas A. Ziaja, Uma Durairajan, Dinesh R. Amirtharaj
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Publication number: 20220139478Abstract: Testability of memory on integrated circuits is improved by connecting storage elements like latches in memory to scan chains and configuring memory for scan dump. The use of latches and similar compact storage elements to form scannable memory can extend the testability of high-density memory circuits on complex integrated circuits operable at high clock speeds. A scannable memory architecture includes an input buffer with active low buffer latches, and an array of active high storage latches, operated in coordination to enable incorporation of the memory into scan chains for ATPG/TT and scan dump testing modes.Type: ApplicationFiled: September 7, 2021Publication date: May 5, 2022Applicant: SambaNova Systems, Inc.Inventors: Thomas A. ZIAJA, Uma DURAIRAJAN, Dinesh R. AMIRTHARAJ
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Publication number: 20220139477Abstract: Testability of memory on integrated circuits is improved by connecting storage elements like latches in memory to scan chains and configuring memory for scan dump. The use of latches and similar compact storage elements to form scannable memory can extend the testability of high-density memory circuits on complex integrated circuits operable at high clock speeds. A scannable memory architecture includes an input buffer with active low buffer latches, and an array of active high storage latches, operated in coordination to enable incorporation of the memory into scan chains for ATPG/TT and scan dump testing modes.Type: ApplicationFiled: September 7, 2021Publication date: May 5, 2022Applicant: SambaNova Systems, Inc.Inventors: Thomas A. ZIAJA, Uma DURAIRAJAN, Dinesh R. AMIRTHARAJ
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Patent number: 10408876Abstract: Embodiments include novel approaches for scan-based device testing using a march controller. A march data store can have sets of march element data stored thereon, each defining a respective march element of a march test sequence. A march select register can select each stored set of march element data according to the predefined march test sequence, and a march data loader can iteratively and sequentially output each set of march element data selected by the march select register. A memory built-in self-test controller can generate, in response to receiving each set of march element data output by the march controller, test stimulus data corresponding to the received set of march element data. The test stimulus data can input to a scan chain of the integrated circuit under test, and response data can be captured from the scan chain and assessed to determine whether the integrated circuit passed the test.Type: GrantFiled: January 29, 2018Date of Patent: September 10, 2019Assignee: ORACLE INTERNATIONAL CORPORATIONInventors: Thomas Ziaja, Lancelot Kwong
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Publication number: 20190235019Abstract: Embodiments include novel approaches for scan-based device testing using a march controller. A march data store can have sets of march element data stored thereon, each defining a respective march element of a march test sequence. A march select register can select each stored set of march element data according to the predefined march test sequence, and a march data loader can iteratively and sequentially output each set of march element data selected by the march select register. A memory built-in self-test controller can generate, in response to receiving each set of march element data output by the march controller, test stimulus data corresponding to the received set of march element data. The test stimulus data can input to a scan chain of the integrated circuit under test, and response data can be captured from the scan chain and assessed to determine whether the integrated circuit passed the test.Type: ApplicationFiled: January 29, 2018Publication date: August 1, 2019Inventors: Thomas Ziaja, Lancelot Kwong
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Patent number: 9401223Abstract: A method and apparatus for conducting at-speed testing of a memory array in an integrated circuit (IC) is disclosed. In one embodiment, an IC includes a memory array and a plurality of input circuits coupled to provide input signals into the memory array. Each of the plurality of input circuits includes an input flip-flop having a data output coupled to a corresponding input of the memory array, selection circuitry configured to select a data path to a data input of the input flip-flop and a data path shift register coupled to control a state of a selection signal provided to the selection circuitry, wherein the data path shift register includes a plurality of multiplexers. When operating the IC in a test mode, the plurality of input circuits is configured to provide input signals into the memory array at an operational clock speed of the IC.Type: GrantFiled: May 9, 2014Date of Patent: July 26, 2016Assignee: Oracle International CorporationInventors: Thomas A Ziaja, Murali M. R. Gala
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Publication number: 20150325314Abstract: A method and apparatus for conducting at-speed testing of a memory array in an integrated circuit (IC) is disclosed. In one embodiment, an IC includes a memory array and a plurality of input circuits coupled to provide input signals into the memory array. Each of the plurality of input circuits includes an input flip-flop having a data output coupled to a corresponding input of the memory array, selection circuitry configured to select a data path to a data input of the input flip-flop and a data path shift register coupled to control a state of a selection signal provided to the selection circuitry, wherein the data path shift register includes a plurality of multiplexers. When operating the IC in a test mode, the plurality of input circuits is configured to provide input signals into the memory array at an operational clock speed of the IC.Type: ApplicationFiled: May 9, 2014Publication date: November 12, 2015Inventors: Thomas A Ziaja, Murali M. R. Gala
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Patent number: 8074133Abstract: An apparatus or method for testing of a SOC processor device may minimize interference that is caused by interfacing a comparatively low-speed testing device with the high-speed processor during testing. Implementations may gate the input clock signal at the clock input to each domain of the SOC processor device rather than at the output of the PLL clock. The gating of the clock signal to each domain may then be controlled by clock stop signals generated by the testing device and sent to the individual domains of the processor device. Gating the clock signal at the domain may provide a more natural state for the circuit during testing as well as allow the test control unit to test the different domains of the SOC device individually.Type: GrantFiled: August 6, 2008Date of Patent: December 6, 2011Assignee: Oracle America, Inc.Inventors: Thomas A. Ziaja, Kevin D. Woodling, Robert F. Molyneaux
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Patent number: 8065572Abstract: An integrated circuit configured for at-speed scan testing of memory arrays. The integrated circuit includes a scan chain having a plurality of serially coupled scan elements, wherein a subset of the plurality of scan elements are coupled to provide signals to a memory array. Each scan element of the subset of the plurality of scan elements includes a flip flop having a data input, and a data output coupled to a corresponding input of the memory array, and selection circuitry configured to, in an operational mode, couple a data path to the data input, and further configured to, in a scan mode, couple to the data input one of a scan input, the data output, and a complement of the data output. The scan elements of the subset support at-speed testing of a memory array coupled thereto.Type: GrantFiled: June 30, 2009Date of Patent: November 22, 2011Assignee: Oracle America, Inc.Inventors: Thomas A. Ziaja, Murali Gala, Paul J. Dickinson, Karl P. Dahlgren, David L. Curwen, Oliver Caty, Steven C. Krow-Lucal, James C. Hunt, Poh-Joo Tan
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Publication number: 20100332924Abstract: An integrated circuit configured for at-speed scan testing of memory arrays. The integrated circuit includes a scan chain having a plurality of serially coupled scan elements, wherein a subset of the plurality of scan elements are coupled to provide signals to a memory array. Each scan element of the subset of the plurality of scan elements includes a flip flop having a data input, and a data output coupled to a corresponding input of the memory array, and selection circuitry configured to, in an operational mode, couple a data path to the data input, and further configured to, in a scan mode, couple to the data input one of a scan input, the data output, and a complement of the data output. The scan elements of the subset support at-speed testing of a memory array coupled thereto.Type: ApplicationFiled: June 30, 2009Publication date: December 30, 2010Inventors: Thomas A. Ziaja, Murali Gala, Paul J. Dickinson, Karl P. Dahlgren, David L. Curwen, Oliver Caty, Steven C. Krow-Lucal, James C. Hunt, Poh-Joo Tan
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Publication number: 20100037111Abstract: An apparatus or method for testing of a SOC processor device may minimize interference that is caused by interfacing a comparatively low-speed testing device with the high-speed processor during testing. Implementations may gate the input clock signal at the clock input to each domain of the SOC processor device rather than at the output of the PLL clock. The gating of the clock signal to each domain may then be controlled by clock stop signals generated by the testing device and sent to the individual domains of the processor device. Gating the clock signal at the domain may provide a more natural state for the circuit during testing as well as allow the test control unit to test the different domains of the SOC device individually.Type: ApplicationFiled: August 6, 2008Publication date: February 11, 2010Applicant: Sun Microsystems, Inc.Inventors: Thomas A. Ziaja, Kevin D. Woodling, Robert F. Molyneaux
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Patent number: 6813201Abstract: Methods and systems for automated memory test modeling generation and validation are provided. Information supplied by a graphical user interface is used to generate a customized memory primitive. The memory primitive subsequently undergoes a two phase validation to test for correct functioning.Type: GrantFiled: October 24, 2001Date of Patent: November 2, 2004Assignee: Sun Microsystems, Inc.Inventors: Kamran Zarrineh, Thomas A. Ziaja, Amitava Majumdar
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Publication number: 20030076723Abstract: Methods and systems for automated memory test modeling generation and validation are provided. Information supplied by a graphical user interface is used to generate a customized memory primitive. The memory primitive subsequently undergoes a two phase validation to test for correct functioning.Type: ApplicationFiled: October 24, 2001Publication date: April 24, 2003Applicant: Sun Microsystems, Inc.Inventors: Kamran Zarrineh, Thomas A. Ziaja, Amitava Majumdar