Patents by Inventor Thomas Aichinger

Thomas Aichinger has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11101343
    Abstract: A semiconductor component has a gate structure that extends from a first surface into an SiC semiconductor body. A body area in the SiC semiconductor body adjoins a first side wall of the gate structure. A first shielding area and a second shielding area of the conductivity type of the body area have at least twice as high a level of doping as the body area. A diode area forms a Schottky contact with a load electrode between the first shielding area and the second shielding area.
    Type: Grant
    Filed: May 6, 2019
    Date of Patent: August 24, 2021
    Assignee: Infineon Technologies AG
    Inventors: Ralf Siemieniec, Thomas Aichinger, Thomas Basler, Wolfgang Bergner, Rudolf Elpelt, Romain Esteve, Michael Hell, Daniel Kueck, Caspar Leendertz, Dethard Peters, Hans-Joachim Schulze
  • Publication number: 20210119006
    Abstract: In an example, a transistor device is provided. The transistor device includes a plurality of transistor cells each including a gate electrode and each at least partially integrated in a semiconductor body that includes a wide bandgap semiconductor material. The transistor device includes a gate pad arranged on top of the semiconductor body, and a plurality of gate runners each arranged on top of the semiconductor body and each connected to gate electrodes of at least some of the plurality of transistor cells. Each gate runner of the plurality of gate runners has a longitudinal direction, and at least one of the gate runners includes at least a section in which a resistivity per area increases in the longitudinal direction as a distance to the gate pad along the gate runner increases.
    Type: Application
    Filed: October 16, 2020
    Publication date: April 22, 2021
    Inventors: Thomas AICHINGER, Wolfgang BERGNER, Ralf SIEMIENIEC, Frank WOLTER
  • Publication number: 20210118986
    Abstract: A semiconductor device includes gate trenches formed in a SiC substrate and extending lengthwise in parallel in a first direction. A trench interval which defines a space between adjacent gate trenches extends in a second direction perpendicular to the first direction. Source regions of a first conductivity type formed in the SiC substrate occupy a first part of the space between adjacent gate trenches. Body regions of a second conductivity type opposite the first conductivity type formed in the SiC substrate and below the source regions occupy a second part of the space between adjacent gate trenches. Body contact regions of the second conductivity type formed in the SiC substrate occupy a third part of the space between adjacent gate trenches. Shielding regions of the second conductivity type formed deeper in the SiC substrate than the body regions adjoin a bottom of at least some of the gate trenches.
    Type: Application
    Filed: December 4, 2020
    Publication date: April 22, 2021
    Inventors: Thomas Aichinger, Wolfgang Bergner, Paul Ellinghaus, Rudolf Elpelt, Romain Esteve, Florian Grasse, Caspar Leendertz, Shiqin Niu, Dethard Peters, Ralf Siemieniec, Bernd Zippelius
  • Patent number: 10896952
    Abstract: A semiconductor device includes gate trenches formed in a SiC substrate and extending lengthwise in parallel in a first direction. A trench interval which defines a space between adjacent gate trenches extends in a second direction perpendicular to the first direction. Source regions of a first conductivity type formed in the SiC substrate occupy a first part of the space between adjacent gate trenches. Body regions of a second conductivity type opposite the first conductivity type formed in the SiC substrate and below the source regions occupy a second part of the space between adjacent gate trenches. Body contact regions of the second conductivity type formed in the SiC substrate occupy a third part of the space between adjacent gate trenches. Shielding regions of the second conductivity type formed deeper in the SiC substrate than the body regions adjoin a bottom of at least some of the gate trenches.
    Type: Grant
    Filed: February 21, 2020
    Date of Patent: January 19, 2021
    Assignee: Infineon Technologies AG
    Inventors: Thomas Aichinger, Wolfgang Bergner, Paul Ellinghaus, Rudolf Elpelt, Romain Esteve, Florian Grasse, Caspar Leendertz, Shiqin Niu, Dethard Peters, Ralf Siemieniec, Bernd Zippelius
  • Patent number: 10734514
    Abstract: A semiconductor device includes trench structures that extend from a first surface into a semiconductor body. The trench structures include a gate structure and a contact structure that extends through the gate structure, respectively. Transistor mesas are between the trench structures. Each transistor mesa includes a body zone forming a first pn junction with a drift structure and a second pn junction with a source zone. Diode regions directly adjoin one of the contact structures form a third pn junction with the drift structure, respectively.
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: August 4, 2020
    Assignee: Infineon Technologies AG
    Inventors: Thomas Aichinger, Romain Esteve, Dethard Peters, Roland Rupp, Ralf Siemieniec
  • Patent number: 10714609
    Abstract: A semiconductor device includes a plurality of gate trenches formed in a first surface of a semiconductor body and extending lengthwise parallel to one another, transistor cells and diode regions formed in a mesa of the semiconductor body between neighboring ones of the gate trenches, and a drift region in the semiconductor body beneath the gate trenches. Each transistor cell includes a source zone and a body region. Each diode region includes a contact portion and a lower doped shielding portion. The source zone forms a first p-n junction with the body region, and the body region forms a second p-n junction with the drift region. The contact region extends to the first surface, and the shielding portion forms a third p-n junction with the drift region. The shielding portion extends under bottoms of the neighboring ones of the gate trenches.
    Type: Grant
    Filed: April 16, 2019
    Date of Patent: July 14, 2020
    Assignee: Infineon Technologies AG
    Inventors: Thomas Aichinger, Dethard Peters, Ralf Siemieniec
  • Patent number: 10700182
    Abstract: By using at least one of a processor device and model transistor cells, a set of design parameters for at least one of a transistor cell and a drift structure of a wide band-gap semiconductor device is determined, wherein an on state failure-in-time rate and an off state failure-in-time rate of a gate dielectric of the transistor cell are within a same order of magnitude for a predefined on-state gate-to-source voltage, a predefined off-state gate-to-source voltage, and a predefined off-state drain-to-source voltage.
    Type: Grant
    Filed: May 14, 2018
    Date of Patent: June 30, 2020
    Assignee: Infineon Technologies AG
    Inventors: Thomas Aichinger, Wolfgang Bergner, Romain Esteve, Daniel Kueck, Dethard Peters, Ralf Siemieniec, Bernd Zippelius
  • Publication number: 20200194544
    Abstract: A semiconductor device includes gate trenches formed in a SiC substrate and extending lengthwise in parallel in a first direction. A trench interval which defines a space between adjacent gate trenches extends in a second direction perpendicular to the first direction. Source regions of a first conductivity type formed in the SiC substrate occupy a first part of the space between adjacent gate trenches. Body regions of a second conductivity type opposite the first conductivity type formed in the SiC substrate and below the source regions occupy a second part of the space between adjacent gate trenches. Body contact regions of the second conductivity type formed in the SiC substrate occupy a third part of the space between adjacent gate trenches. Shielding regions of the second conductivity type formed deeper in the SiC substrate than the body regions adjoin a bottom of at least some of the gate trenches.
    Type: Application
    Filed: February 21, 2020
    Publication date: June 18, 2020
    Inventors: Thomas Aichinger, Wolfgang Bergner, Paul Ellinghaus, Rudolf Elpelt, Romain Esteve, Florian Grasse, Caspar Leendertz, Shiqin Niu, Dethard Peters, Ralf Siemieniec, Bernd Zippelius
  • Publication number: 20200176580
    Abstract: A silicon carbide device includes a silicon carbide substrate having a body region and a source region of a transistor cell. Further, the silicon carbide device includes a titanium carbide gate electrode of the transistor cell.
    Type: Application
    Filed: November 25, 2019
    Publication date: June 4, 2020
    Inventors: Ralf Siemieniec, Thomas Aichinger, Iris Moder, Francisco Javier Santos Rodriguez, Hans-Joachim Schulze, Carsten von Koblinski
  • Publication number: 20200098868
    Abstract: An embodiment of a semiconductor device includes a trench gate structure extending from a first surface into a silicon carbide semiconductor body along a vertical direction. A body region of a first conductivity type adjoins a sidewall of the trench gate structure and includes a first body sub-region adjoining the sidewall and a second body sub-region adjoining the sidewall. At least one profile of dopants of the first conductivity type along the vertical direction includes a first doping peak in the first body sub-region and a second doping peak in the second body sub-region. A doping concentration of the first doping peak is larger than a doping concentration of the second doping peak.
    Type: Application
    Filed: September 19, 2019
    Publication date: March 26, 2020
    Inventors: Reinhard Ploss, Thomas Aichinger, Roland Rupp, Hans-Joachim Schulze
  • Patent number: 10586845
    Abstract: According to an embodiment of a semiconductor device, the device includes gate trenches formed in a SiC substrate and extending lengthwise in parallel in a first direction. Rows of source regions of a first conductivity type are formed in the SiC substrate and extend lengthwise in parallel in a second direction which is transverse to the first direction. Rows of body regions of a second conductivity type opposite the first conductivity type are formed in the SiC substrate below the rows of source regions. Rows of body contact regions of the second conductivity type are formed in the SiC substrate. The rows of body contact regions extend lengthwise in parallel in the second direction. First shielding regions of the second conductivity type are formed deeper in the SiC substrate than the rows of body regions.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: March 10, 2020
    Assignee: Infineon Technologies AG
    Inventors: Thomas Aichinger, Wolfgang Bergner, Paul Ellinghaus, Rudolf Elpelt, Romain Esteve, Florian Grasse, Caspar Leendertz, Shiqin Niu, Dethard Peters, Ralf Siemieniec, Bernd Zippelius
  • Patent number: 10553685
    Abstract: A semiconductor device includes a trench extending from a first surface into a SiC semiconductor body. The trench has a first sidewall, a second sidewall opposite to the first sidewall, and a trench bottom. A gate electrode is arranged in the trench and is electrically insulated from the SiC semiconductor body by a trench dielectric. A body region of a first conductivity type adjoins the first sidewall. A shielding structure of the first conductivity type adjoins at least a portion of the second sidewall and the trench bottom. A first section of the trench bottom and a second section of the trench bottom are offset to one another by a vertical offset along a vertical direction extending from the first surface to a second surface of the SiC semiconductor body opposite to the first surface.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: February 4, 2020
    Assignee: Infineon Technologies AG
    Inventors: Ralf Siemieniec, Thomas Aichinger, Romain Esteve, Daniel Kueck
  • Publication number: 20200006544
    Abstract: A semiconductor device includes a silicon carbide body including a transistor cell region and an idle region. The transistor cell region includes transistor cells. The idle region is devoid of transistor cells. The idle region includes a transition region between the transistor cell region and a side surface of the silicon carbide body, a gate pad region, and a diode structure comprising at least one of a merged pin Schottky diode structure or a merged pin heterojunction diode structure in at least one of the transition region or the gate pad region.
    Type: Application
    Filed: June 27, 2019
    Publication date: January 2, 2020
    Inventors: Ralf SIEMIENIEC, Thomas AICHINGER, Wolfgang BERGNER, Romain ESTEVE, Daniel KUECK, Dethard PETERS, Bernd ZIPPELIUS
  • Publication number: 20190355819
    Abstract: A semiconductor device includes a gate electrode and a gate dielectric. The gate electrode extends from a first surface of a silicon carbide body into the silicon carbide body. The gate dielectric is between the gate electrode and the silicon carbide body. The gate electrode includes a metal structure and a semiconductor layer between the metal structure and the gate dielectric.
    Type: Application
    Filed: May 14, 2019
    Publication date: November 21, 2019
    Inventors: Ralf Siemieniec, Thomas Aichinger, Romain Esteve, Ravi Keshav Joshi, Shiqin Niu
  • Publication number: 20190341447
    Abstract: A semiconductor component has a gate structure that extends from a first surface into an SiC semiconductor body. A body area in the SiC semiconductor body adjoins a first side wall of the gate structure. A first shielding area and a second shielding area of the conductivity type of the body area have at least twice as high a level of doping as the body area. A diode area forms a Schottky contact with a load electrode between the first shielding area and the second shielding area.
    Type: Application
    Filed: May 6, 2019
    Publication date: November 7, 2019
    Inventors: Ralf Siemieniec, Thomas Aichinger, Thomas Basler, Wolfgang Bergner, Rudolf Elpelt, Romain Esteve, Michael Hell, Daniel Kueck, Caspar Leendertz, Dethard Peters, Hans-Joachim Schulze
  • Publication number: 20190311903
    Abstract: A method for forming a wide band gap semiconductor device is provided. The method includes forming a gate insulation layer on a wide band gap semiconductor substrate and annealing the gate insulation layer using at least a first reactive gas species and a second reactive gas species, wherein the first reactive gas species differs from the second reactive gas species. The method can include forming a gate electrode on the gate insulation layer after annealing the gate insulation layer.
    Type: Application
    Filed: April 3, 2019
    Publication date: October 10, 2019
    Inventors: Thomas Aichinger, Gerald Rescher, Michael Stadtmueller
  • Patent number: 10393697
    Abstract: An apparatus for analyzing ion kinetics in a dielectric probe structure includes an ion reservoir abutting the dielectric probe structure and configured to supply mobile ions to the dielectric probe structure, a capacitor structure configured to generate an electric field in the dielectric probe structure along a vertical direction, and an electrode structure configured to generate an electrophoretic force on mobile ions in the dielectric probe structure along a lateral direction. A method for analyzing ion kinetics in the dielectric probe structure of the apparatus is also provided.
    Type: Grant
    Filed: November 2, 2015
    Date of Patent: August 27, 2019
    Assignee: Infineon Technologies AG
    Inventors: Sabine Gruber, Thomas Aichinger, Stefan Krivec, Thomas Ostermann
  • Publication number: 20190245075
    Abstract: A semiconductor device includes a plurality of gate trenches formed in a first surface of a semiconductor body and extending lengthwise parallel to one another, transistor cells and diode regions formed in a mesa of the semiconductor body between neighboring ones of the gate trenches, and a drift region in the semiconductor body beneath the gate trenches. Each transistor cell includes a source zone and a body region. Each diode region includes a contact portion and a lower doped shielding portion. The source zone forms a first p-n junction with the body region, and the body region forms a second p-n junction with the drift region. The contact region extends to the first surface, and the shielding portion forms a third p-n junction with the drift region. The shielding portion extends under bottoms of the neighboring ones of the gate trenches.
    Type: Application
    Filed: April 16, 2019
    Publication date: August 8, 2019
    Inventors: Thomas Aichinger, Dethard Peters, Ralf Siemieniec
  • Patent number: 10304953
    Abstract: A semiconductor device includes stripe-shaped trench gate structures that extend in a semiconductor body along a first horizontal direction. Transistor mesas between neighboring trench gate structures include body regions and source zones, wherein the body regions form first pn junctions with a drift structure and second pn junctions with the source zones. The source zones directly adjoin two neighboring trench gate structures, respectively. Diode mesas that include at least portions of diode regions form third pn junctions with the drift structure. The diode mesas directly adjoin two neighboring trench gate structures, respectively. The transistor mesas and the diode mesas alternate at least along the first horizontal direction.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: May 28, 2019
    Assignee: Infineon Technologies AG
    Inventors: Thomas Aichinger, Dethard Peters, Ralf Siemieniec
  • Patent number: 10217636
    Abstract: A trench is formed that extends from a main surface into a crystalline silicon carbide semiconductor layer. A mask is formed that includes a mask opening exposing the trench and a rim section of the main surface around the trench. By irradiation with a particle beam a first portion of the semiconductor layer exposed by the mask opening and a second portion outside of the vertical projection of the mask opening and directly adjoining to the first portion are amorphized. A vertical extension of the amorphized second portion gradually decreases with increasing distance to the first portion. The amorphized first and second portions are removed.
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: February 26, 2019
    Assignee: Infineon Technologies AG
    Inventors: Thomas Aichinger, Victorina Poenariu, Wolfgang Bergner, Romain Esteve, Daniel Kueck, Dethard Peters, Gerald Reinwald, Roland Rupp, Gerald Unegg