Abstract: A method for improving data processing in an L2 cache for symmetrical multiprocessing systems consists of efficient execution of cache control instructions without having to give up the data bandwidth provided by a greater byte coherency granule. The L2 cache has a coherency granule size within its data array and is divided into a target sector and an alternate sector. Additionally, the coherency granule has a plurality of MESI bits, which define sector write enables, and data write enables. By determining the states of the target sector and/or the alternate sector a series of L2 cache control instructions are performed to signal the L2 cache to hit. If a hit occurs corresponding data will be either written into or read out of the data array.

Abstract: Storage access blocking instructions, such as the EIEIO instruction implemented within the PowerPC architecture, block other storage access instructions at the bus interface stage as opposed to the execute stage. Therefore, cacheable instructions, and other similar instructions, are allowed to complete without being blocked by such an EIEIO instruction not ordered by the EIEIO instruction.

Abstract: Described is an apparatus for eliminating early retrying of PAAM address conflicts on a system bus with multiple processors connected by a non-master processor, by comparing addresses of the current master processor to the next transaction to be issued by the non-master processor. If the addresses are the same and a PAAM window is detected, the non-master processor will switch the next transaction type to be issued, to a null type transaction. Even though the addresses match, the PAAM window is ignored for a null type transaction. The null transaction type insertion by the non-master processor reduces the latency of a PAAM self retried operation and avoids a possible livelock condition by breaking the processors out of the livelock. This allows the processors to stop retrying and leave the bus. The processors are able to immediately arbitrate instead of delaying past the astat window and increasing bus latency.

Abstract: A data processing system includes at least a first processor and a second processor that each have a respective translation lookaside buffer (TLB). In response to detection by the second processor of a TLB entry invalidation request, the second processor marks at least one memory referent instruction that is being processed by the second processor and invalidates a TLB entry in the TLB of the second processor. In response to receipt of a synchronization request at the second processor, the second processor indicates to the first processor that the second processor has invalidated the TLB entry if the second processor has completed processing the marked instruction. During the interval between receipt of the synchronization request and indicating to the first processor that the second processor has invalidated the TLB entry, the second processor continues to process instructions, including fetching instructions for processing.

Abstract: To implement full gathering of data transfers from a processor to a system bus without adding many levels of logic to the write enable logic for transaction queue entries or reducing the processor operating frequency, gatherable combinations are divided and gathering is performed in multiple stages operating in parallel. During the first stage, a subset of the full gathering is performed between incoming transactions and the last transaction received, coalescing the two transfers into a single transaction entry if one of the possible combinations within the subset is satisfied. During the second stage, existing queue entries are tested for the remainder of the full gather combination set and merged if a combination within the remaining subset is satisfied.