Abstract: Methods, systems, and devices for error detection, error correction, and error management by memory devices are described. Programmable thresholds may be configured for a memory device based on a type of data or a location of stored data, among other aspects. For example, a host device may configure a threshold quantity of errors for data at a memory device. When retrieving the data, the memory device may track or count errors in the data and determine whether the threshold has been satisfied. The memory device may transmit (e.g., to the host device) an indication whether the threshold has been satisfied, and the system may perform functions to correct the errors and/or prevent further errors. The memory device may also identify errors in received commands or may identify errors introduced in data after the data was received (e.g., using an error detecting code associated with a command or bus).

Abstract: The invention relates to method of manufacturing a recess wall lined with bristles for a mouthpiece for simultaneously brushing at a plurality of dental positions, and to a recess wall and mouthpiece manufactured according to the method. In a providing step, an elongate, continuous, bristled sheet part having a first side lined with a plurality of bristles is provided. The elongate sheet part defines a length axis extending parallel to the sheet part and, viewed transverse to the length axis, a cross-sectional shape. The sheet part obtained in the providing step has an initial condition in which the cross-sectional shape has an initial shape, and the length axis is arch-shaped. In a transforming step, the sheet part of the providing step is transformed from the initial condition to a final condition to provide the recess wall. In the final condition the cross-sectional shape has a final U-shape, the length axis is arch shaped, and the first side is a concave inner side of the final U-shape.

Abstract: Methods, systems, and devices for signal path biasing in an electronic system (e.g., a memory system) are described. In one example, a memory device, a host device, or both may be configured to bias a signal path, between an idle state and an information transfer or between an information transfer and an idle state, to an intermediate or mid-bias voltage level, which may reduce signal interference associated with such transitions. In various examples, the described biasing to a voltage, such as a mid-bias voltage, may be associated with an access command or other command for information to be communicated between devices of the electronic system, such as a command for information to be communicated between a memory device and a host device.

Abstract: A hardware state machine connected to a processor, the hardware state machine configured to receive operational codes from the processor; a multiplexer connected to the processor, the hardware state machine and a checksum circuit, the multiplexer configured to receive data from the processor; and a transmit circuit connected to the multiplexer, the transmit circuit configured to receive data from the multiplexer for transmission to a far end device, wherein the hardware state machine is further configured to, responsive receiving one or more operational codes from the processor: cause the checksum circuit to alter a checksum value of a first data packet being transmitted by the transmit circuit; and cause the transmit circuit to preempt transmission of the first data packet and begin transmitting a second data packet once the checksum value so altered has been transmitted from the transmit circuit.

Abstract: Methods, systems, and devices for channel modulation for a memory device are described. A system may include a memory device and a host device coupled with the memory device. The system may be configured to communicate a first signal modulated using a first modulation scheme and communicate a second signal that is based on the first signal and that is modulated using a second modulation scheme. The first modulation scheme may include a first quantity of voltage levels that span a first range of voltages, and the second modulation scheme may include a second quantity of voltage levels that span a second range of voltages different than (e.g., smaller than) the first range of voltages. The first signal may include write data carried over a data channel, and the second signal may include error detection information based on the write data that is carried over an error detection channel.

Abstract: A method, computer system, and a computer program product for storing a graph is provided. The present invention may include providing a key-value store. The present invention may include storing a graph in the key-value store, wherein storing a specific node of the graph in the key-value store comprises: storing, as a key, identifiers of the specific node and of k-hop neighborhood of the specific node, and as value of the key, attribute values of the specific node, wherein the k-hop neighborhood of the specific node comprises a set of neighboring nodes that are reachable from the specific node within k edges.

Abstract: Methods, systems, and devices for masked training and analysis with a memory array are described. A memory device may operate in a first mode in which a maximum transition avoidance (MTA) decoder for a memory array of the memory device is disabled. During the first mode, the memory device may couple an input node of the MTA decoder with a first output node of a first decoder, such as a first pulse amplitude modulation (PAM) decoder. The memory device may operate in a second mode in which the MTA decoder for the memory array is enabled. During the second mode, the memory device may couple the input node of the MTA decoder with a second output node of a second decoder, such as a second PAM decoder.

Abstract: Systems, apparatuses, and methods for transmission failure feedback associated with a memory device are described. A memory device may detect errors in received data and transmit an indication of the error when detected. The memory device may receive data and checksum information for the data from a controller. The memory device may generate a checksum for the received data and may detect transmission errors. The memory device may transmit an indication of detected errors to the controller, and the indication may be transmitted using a line that is different than an error detection code (EDC) line. A low-speed tracking clock signal may also be transmitted by the memory device over a line different than the EDC line. The memory device may transmit a generated checksum to the controller with a time offset applied to the checksum signaled over the EDC line.

Abstract: A process for the epoxidation of propene involves reacting propene with hydrogen peroxide, in the presence of a methanol solvent and a shaped titanium zeolite epoxidation catalyst in a fixed bed reactor. The process then involves recovering methanol from the reaction mixture, treatment of the recovered methanol by passing it through a bed of an acidic ion exchange resin, and recycling the treated methanol to the epoxidation reaction; as well as regeneration of the acidic ion exchange resin. Catalyst breakage can be reduced or avoided by washing the regenerated bed of an acidic ion exchange resin with methanol until the methanol exiting the resin bed has an apparent pH higher than 1.8, before methanol treated with the acidic ion exchange resin is recycled to the epoxidation reaction.

Abstract: The invention provides a process for regenerating a catalyst used for the hydrogenation of an aromatic species, consisting of several steps. First the system is purged with nitrogen, then air is metered in stepwise, and the addition of nitrogen is subsequently ended until only air is present.

Abstract: Methods, systems, and devices for error detection, error correction, and error management by memory devices are described. Programmable thresholds may be configured for a memory device based on a type of data or a location of stored data, among other aspects. For example, a host device may configure a threshold quantity of errors for data at a memory device. When retrieving the data, the memory device may track or count errors in the data and determine whether the threshold has been satisfied. The memory device may transmit (e.g., to the host device) an indication whether the threshold has been satisfied, and the system may perform functions to correct the errors and/or prevent further errors. The memory device may also identify errors in received commands or may identify errors introduced in data after the data was received (e.g., using an error detecting code associated with a command or bus).

Abstract: An x-ray tube includes a housing containing cooling oil and a vacuum envelope disposed within the housing and including a solid envelope wall. The oil is disposed between the housing and wall. An anode and cathode are arranged in a vacuum environment and surrounded by the wall. A rotor connected to the anode is arranged on bearings within the vacuum environment. Additionally, a stator assembly positioned within the oil surrounds the rotor to define an oil-filled annular gap. The stator assembly includes a stator core, stator teeth spaced apart by intervening stator slots, and stator windings disposed within the stator slots. Each stator tooth includes a tooth tip positioned adjacent to the boundary wall and set a distance apart from the stator windings to form an intra-slot cooling channel in fluid communication with the oil-filled annular gap such that the stator teeth inclusive of its tooth tips are immersed in oil.

Abstract: A spinlock circuit connected to one or more first processors through one or more broadside interfaces. The spinlock circuit is configured to receive a plurality of requests for use of a computing resource from one or more first processors, and reply to each of the plurality of requests within a single clock cycle of the one or more first processors. The spinlock circuit can reply to each of the plurality of requests within a single clock cycle of the one or more first processors by alternately assigning the computing resource to a requesting processor from among the one or more first processors or indicating to the requesting processor from among the one or more first processors that the computing resource is not available.

Abstract: A roof system for a vehicle comprises a wind deflector member including a wind deflector body which extends in a transverse direction of the vehicle that is movable between a retracted position below a fixed roof and an extended position at least partly above the fixed roof. Wind deflector arms at the lateral ends of the wind deflector body extend substantially in a rearward direction and are at least rotatably connected to a stationary part. A sealing arrangement comprises a first seal is positioned between the wind deflector body and a panel that seals a gap between an the wind deflector body and the panel in its closed position. The first seal is configured to close a gap between the wind deflector arms and the panel. A second seal is closes a gap between the wind deflector member and the stationary part when the panel is in its closed position.

Abstract: An open roof construction for a vehicle comprises at least a movable lever to which, by means of a pin-like member, a slide shoe is connected that, for defining a movement of the movable lever, cooperates with and moves longitudinally along a guide. The pin-like member at a first end is connected to said lever and at a second end is connected to said slide shoe and the guide and slide shoe are provided with at least one pair of cooperating guide part and slide shoe part. The pin-like member at its second end is provided with an enlarged head configured to engage the slide shoe at a side thereof facing away from the lever. The dimensions of the enlarged head are such that, as seen in a direction from the enlarged head towards the lever, at least part of said enlarged head overlaps at least one guide part.

Abstract: A real-time computational device includes a programmable real-time processor, a communications input port which is connected to the programmable real-time processor through a first broadside interface, and a communications output port which is connected to the programmable real-time processor through a second broadside interface. Both broadside interfaces enable 1024 bits of data to be transferred across each of the broadside interfaces in a single clock cycle of the programmable real-time processor.

Abstract: A vehicle includes a roof construction comprising at least one semi-transparent panel fitted in an opening in the fixed roof of the vehicle. The panel is connected to a stationary frame. A headliner on the interior side of the fixed roof is provided for hiding the fixed roof and stationary frame from view. At least one display device is capable of showing images from its display screen to occupants in the vehicle. A drive system is provided for moving the display screen at least into a storage position and into an operational position in which the display screen is visible for occupants in an interior space of the vehicle. The display screen, in its storage position, is moved into a cavity above the headliner and is thus hidden from view and protected by the headliner.

Abstract: A panel for use in an open roof construction for a vehicle comprises a substantially rectangular panel main body made of transparent material, and at least one elongated reinforcing bracket positioned at least partly in the vicinity of an edge of said panel main body and firmly connected thereto. The panel bracket is made of a material which is thinner than that of the material of the panel main body and includes a structure to fix the reinforcing bracket to an operating mechanism configured to support the panel and control movements thereof. The edge of the panel main body comprises at least an inward recess and the reinforcing bracket comprises at least an upward step into the recess. The upward step extends along at least a portion of the recess and is dimensioned to accommodate a part of the operating mechanism under it.

Abstract: A computational system includes one or more processors. Each processor has multiple registers, as well attached memory to hold instructions. The processor is coupled to one or more broadside interfaces. A broadside interface allows the processor to load or store an entire widget state in a single clock cycle of the processor. The broadside interface also allows the processor to move and store 32 bytes of information into RAM in less than four to five clock cycles of the processor while the processor concurrently performs one or more mathematical operations on the information while the move and store operation is taking place.

Abstract: A roof system for a vehicle comprises a wind deflector member including a wind deflector body which extends in a transverse direction of the vehicle that is movable between a retracted position below a fixed roof and an extended position at least partly above the fixed roof. Wind deflector arms at the lateral ends of the wind deflector body extend substantially in a rearward direction and are at least rotatably connected to a stationary part. A sealing arrangement comprises a first seal is positioned between the wind deflector body and a panel that seals a gap between an the wind deflector body and the panel in its closed position. The first seal is configured to close a gap between the wind deflector arms and the panel. A second seal is closes a gap between the wind deflector member and the stationary part when the panel is in its closed position.