Abstract: A switched distributed power amplifier includes an amplifier stage that includes a first amplifier subsection and a second amplifier subsection, both including one or more field effect transistors (FETs). Each FET in the first amplifier subsection is coupled to a radio frequency (RF) input terminal. Each FET in the second amplifier subsection is coupled to the RF input terminal through an input delay element, which includes a first inductor, a first capacitance associated with gates of the FETs in the first amplifier subsection, a second capacitance associated with gates of the FETs in the second amplifier subsection, and a third capacitance associated with a capacitor coupled to the RF input terminal. The input delay element is designed such that the sum of the first and third capacitances is equal to the second capacitance. A shunt switch prevents the second amplifier subsection from turning on during a low power mode.

Abstract: An amplifier bias system. The amplifier bias system includes a battery voltage supply coupled with an amplifier transistor to be biased; an output node coupled with a gate of the amplifier transistor; and a current source coupled with the battery voltage supply, wherein the current source provides a current to a node in response to the battery voltage supply. The amplifier bias system further includes a first transistor coupled between the battery voltage supply and the output node, the first transistor having a gate coupled with the first node; a second transistor coupled with the first node, the second transistor having a gate coupled with the output node; and a current load coupled with the output node.

Abstract: Described herein are representative embodiments of amplifiers having selectable power output while maintaining low power consumption. In certain exemplary embodiments, the amplifiers are operated as linear power amplifiers, such as may be used in wireless communication systems. According to one exemplary embodiment, a circuit is described comprising a control system configured to operate the circuit in at least a first mode and a second mode. The circuit of this embodiment further includes a first amplifier section configured to amplify at least a portion of an input signal and produce a first amplified signal on a first signal path in the first mode of operation, a second amplifier section configured to amplify at least a portion of an input signal and produce a second amplified signal on a second signal path in the second mode of operation, and an impedance inverter having an input coupled to the first and second signal paths.

Abstract: A bias control system for the radio frequency power amplifiers that includes a current source, a mirror current, and a bias voltage.

Abstract: Embodiments of methods, apparatus, devices and/or systems associated with bipolar junction transistor are disclosed.

Abstract: A power amplifier having a first amplifier output stage and a parallel second amplifier output stage is provided. The first amplifier output stage is enabled (i.e., fully biased) during both high power and low power operating modes. The second amplifier output stage is disabled during the low power operating mode, and enabled during the high power operating mode. Because neither the first nor second amplifier output stage is operated in an extremely low quiescent current state, the linearity of the power amplifier is maintained for both high power and low power operating modes.

Abstract: An RF transmitter provides both GSM and EDGE capability by implementing collector voltage control over the power transistor(s) in a power amplifier. During EDGE mode, linear base-biasing a power amplifier (PA) allows collector control to provide either saturated mode PA operation (during ramp up/ramp down) or linear mode PA operation (during data burst). Collector control can therefore be used to provide the accurate ramp up and ramp down profiles required for both GSM and EDGE burst output signals, and can also be used to set the level of the constant envelope data burst of a GSM burst output signal, while linear mode PA operation can provide the non-constant envelope EDGE data burst. A variable gain amplifier is used to adjust the input signal to the power amplifier such that the desired transmission level is achieved.

Abstract: A sense transistor is placed in a current path between a reference voltage source and ground. The base terminal of the sense transistor is coupled to the base terminal of an amplifying transistor. Thus, current in the sense transistor corresponds to signal power output by the amplifying transistor. The sense current causes a sense voltage at the collector terminal of the sense transistor. This sense voltage is applied to one input of an error amplifier. The other error amplifier input receives a power control voltage. The error amplifier output is routed back to the base terminal of the amplifying transistor in a negative feedback loop, thereby keeping the power of the signal output by the amplifying transistor at a constant level. In some embodiments the error amplifier output is made independent of changes in the reference voltage. Multiple pairs of corresponding amplifying and sense transistors can be used.