Abstract: A voltage regulator including a first, second, and third capacitances, first switches, and second switches. A first terminal of the first capacitance is connected to a first output. The first output is at a first output voltage. A first terminal of the second capacitance is connected to a second output. The second output is at a second output voltage. The first switches connect a first terminal of the third capacitance to a voltage supply, the first output, or the second output. The second switches connect a second terminal of the third capacitance to a reference terminal, the first output, or the second output. The first and second switches are controlled, based on the first output voltage and the second output voltage, to: adjust voltages across the first, second, and third capacitances; maintain the first output at a first predetermined voltage; and maintain the second output at a second predetermined voltage.

Abstract: A voltage regulator including a first, second, and third capacitances, first switches, and second switches. A first terminal of the first capacitance is connected to a first output. The first output is at a first output voltage. A first terminal of the second capacitance is connected to a second output. The second output is at a second output voltage. The first switches connect a first terminal of the third capacitance to a voltage supply, the first output, or the second output. The second switches connect a second terminal of the third capacitance to a reference terminal, the first output, or the second output. The first and second switches are controlled, based on the first output voltage and the second output voltage, to: adjust voltages across the first, second, and third capacitances; maintain the first output at a first predetermined voltage; and maintain the second output at a second predetermined voltage.

Abstract: An apparatus includes a first switch coupled to a first voltage reference and a second switch coupled to a second voltage reference. A third switch is coupled to a first terminal of a first capacitor and a first terminal of a second capacitor. A fourth switch is coupled to a second terminal of the first capacitor and the first terminal of the second capacitor. A fifth switch is coupled to the second terminal of the first capacitor and a first terminal of a third capacitor. A sixth switch is coupled to the first terminal of the first capacitor and the first terminal of the third capacitor. The first switch, the second switch, the third switch, the fourth switch, the fifth switch, and the sixth switch are controlled to maintain a first voltage level at a first output and a second voltage level at a second output.

Abstract: Apparatus having corresponding methods and non-transitory computer-readable media comprise an amplifier configured to amplify signals according to a bias current, wherein the signals represent packets of data; a packet module configured to recover the packets of data from the signals amplified by the amplifier; and a control module configured to control the bias current according to one or more characteristics of the packets of data.

Abstract: A voltage sensing module for an integrated circuit (IC) that supports operation at a plurality of different voltage levels includes a voltage generation module that generates first and second voltages based on an operating voltage level of the IC. A comparing module receives the first and second voltages and generates a voltage determination signal based on the first and second signals. The voltage determination signal selectively configures an input/output I/O pad of the IC.

Abstract: A pipelined analog to digital converter that includes a first stage and a second stage. The first stage is configured to (i) receive a first phase component and a second phase component and (ii) generate a first integrated component and a second integrated component. The second stage is configured to sample and integrate the first integrated component and the second integrated component. The first stage is configured to: sample the first phase component to generate a first sampled component; sample the second phase component to generate a second sampled component; during a first portion of a first clock phase, (i) sample the first phase component and (ii) integrate the second sampled component to generate the second integrated component; and during a second portion of the first clock phase, (i) sample the second phase component and (ii) integrate the first sampled component to generate the first integrated component.

Abstract: An apparatus includes a first switch coupled to a first voltage reference and a second switch coupled to a second voltage reference. A third switch is coupled to a first terminal of a first capacitor and a first terminal of a second capacitor. A fourth switch is coupled to a second terminal of the first capacitor and the first terminal of the second capacitor. A fifth switch is coupled to the second terminal of the first capacitor and a first terminal of a third capacitor. A sixth switch is coupled to the first terminal of the first capacitor and the first terminal of the third capacitor. The first switch, the second switch, the third switch, the fourth switch, the fifth switch, and the sixth switch are controlled to maintain a first voltage level at a first output and a second voltage level at a second output.

Abstract: Apparatus having corresponding methods and non-transitory computer-readable media comprise an amplifier configured to amplify signals according to a bias current, wherein the signals represent packets of data; a packet module configured to recover the packets of data from the signals amplified by the amplifier; and a control module configured to control the bias current according to one or more characteristics of the packets of data.

Abstract: An I/Q calibration system for a quadrature amplitude modulation (QAM) mode transceiver includes a signal generator that generates reference in-phase (I) and quadrature (Q) signals. An I/Q mismatch compensation module generates compensated I and Q signals based on the reference I and Q signals and amplitude and phase correction signals. An I/Q mismatch calibration module generates the amplitude and phase correction signals. A phase stepper module varies a phase of the reference I and Q signals based on the amplitude and phase correction signals.

Abstract: A comparator circuit includes a bias stage, a first current source, a second current source, and a comparator stage. The bias stage includes a first input, a second input, an output that generates a bias voltage, and a first load, wherein differential reference voltages are applied to the first and second inputs. The first current source generates a bias current based on the bias voltage and inputs the bias current to the bias stage. The second current source generates the bias current based on the bias voltage. The comparator stage communicates with the second current source and includes a first input, a second input, and a second load, wherein differential input voltages are applied to the first and second inputs of the comparator stage. The comparator circuit compares the differential input voltages to the differential reference voltages based on the bias current, the first load, and the second load.

Abstract: A sample and integrate circuit includes first and second switching devices. A first terminal of the first switching device communicates with a first input voltage when the first switching device is in the second state. The first terminal of the first switching device communicates with a first voltage reference when the first switching device is in the first state. A first capacitance communicates with the second terminal of the first switching device. A first terminal of the second switching device communicates with a second input voltage when the second switching device is in the first state. The first terminal of the second switching device communicates with a second voltage reference when the second switching device is in the second state. A first input of an amplifier communicates with the first capacitance and a second capacitance. A second input of the amplifier communicates with a third capacitance and a fourth capacitance.

Abstract: Circuits, systems, and methods for generating a delayed clock signal. The circuit generally includes a first ramp generator configured to produce a first ramp signal in response to a reference clock signal, a first comparison circuit configured to compare the first ramp signal to a first threshold value in response to the reference clock signal to produce a comparison signal, a second ramp generator configured to produce a second ramp signal in response to the comparison signal, and a second comparison circuit configured to compare the second ramp signal to a second threshold value to produce the delayed clock signal.

Abstract: A pipelined analog to digital converter comprises N stages, wherein N is an integer greater than one. A sample and integrate circuit communicates with at least two stages of the N stages. The sample and integrate circuit selectively samples a first voltage input to one of the at least two stages while integrating a difference between a sampled second voltage input of another one of the at least two stages and a second reference voltage to generate a second residue. The sample and integrate circuit selectively integrates a difference between the sampled first voltage and a first reference voltage to generate a first residue while sampling a second voltage input.

Abstract: A pipelined analog to digital converter comprises N stages, wherein N is an integer greater than one. A sample and integrate circuit communicates with at least two stages of the N stages. The sample and integrate circuit selectively samples a first voltage input to one of the at least two stages while integrating a difference between a sampled second voltage input of another one of the at least two stages and a second reference voltage to generate a second residue. The sample and integrate circuit selectively integrates a difference between the sampled first voltage and a first reference voltage to generate a first residue while sampling a second voltage input.

Abstract: Oscillator circuits for reducing phase noise are described in this disclosure. In one embodiment, an oscillator circuit includes a pair of cross-coupled transistors, including a first transistor and a second transistor, a first inductor in communication with a control terminal of the first transistor and an output terminal of the second transistor, a second inductor in communication with a control terminal of the second transistor and an output terminal of the first transistor, and a tank circuit in communication with the first inductor and the second inductor, where the tank circuit comprises a tank inductor and a variable capacitor.

Abstract: A multistage analog circuit for independently controlling a bias current in each stage of the multistage analog circuit having an input stage, an intermediate stage, and an output stage, includes a first current source which controls the input stage of the circuit, a second current source which controls the intermediate stage of the circuit, and a third current source which controls the output stage of the circuit. The bias current in each stage of the circuit is set by the first, second, and third current sources. An output voltage of the circuit is capable of remaining the same when the first current source is changed to affect an input transconductance of the circuit.

Abstract: A single-chip CMOS direct conversion transceiver includes an RF circuit, a transmitter having a synthesizer, a receiver having a baseband filter, and a demodulator. The synthesizer is coupled to the RF circuit. The baseband filter is coupled to the RF circuit and the synthesizer. The demodulator is coupled to the baseband filter. The RF circuit, the synthesizer, the baseband filter, and the demodulator are arranged and configured in CMOS devices and provide a complete interface between an antenna and a voiceband codec.

Abstract: An antenna interface for a Time Division Duplex (TDD) radio transceiver allows a transceiver to be attached to an antenna/filter without the need for an antenna switch. The antenna interface includes a single Balun circuit to convert a single-ended signal to/from differential signals, and a single impedance matching circuit to match an impedance at an output of the single Balun circuit with an input impedance of a Low Noise Amplifier (LNA) of a receiver and to provide an output impedance of a Power Amplifier (PA) of a transmitter. The single impedance matching circuit is coupled to both the LNA and the PA. The LNA and the PA are based on CMOS technology and made within a single integrated circuit.

Abstract: A multistage analog circuit for independently controlling a bias current in each stage of the multistage analog circuit having an input stage, an intermediate stage, and an output stage, includes a first current source which controls the input stage of the circuit, a second current source which controls the intermediate stage of the circuit, and a third current source which controls the output stage of the circuit. The bias current in each stage of the circuit is set by the first, second, and third current sources. An output voltage of the circuit is capable of remaining the same when the first current source is changed to affect an input transconductance of the circuit.

Abstract: A multistage analog circuit for independently controlling a bias current in each stage of the multistage analog circuit having an input stage, an intermediate stage, and an output stage, includes a first current source which controls the input stage of the circuit, a second current source which controls the intermediate stage of the circuit, and a third current source which controls the output stage of the circuit. The bias current in each stage of the circuit is set by the first, second, and third current sources. An output voltage of the circuit is capable of remaining the same when the first current source is changed to affect an input transconductance of the circuit.