Abstract: A prefetch mechanism using prefetch attributes is disclosed. In one aspect, an explicit request for data stored in a memory is provided, and a prefetch attribute in a page table entry associated with the explicit request is examined to determine whether to provide one or more prefetch requests based on the prefetch attribute. Another aspect includes determining dynamic prefetch attributes for use in prefetching data, in which prefetch attributes are adjusted based on memory access requests that target next sequential blocks of memory relative to the most recent previous access in a page of memory.

Abstract: A prefetch mechanism using prefetch attributes is disclosed. In one aspect, an explicit request for data stored in a memory is provided, and a prefetch attribute in a page table entry associated with the explicit request is examined to determine whether to provide one or more prefetch requests based on the prefetch attribute. Another aspect includes determining dynamic prefetch attributes for use in prefetching data, in which prefetch attributes are adjusted based on memory access requests that target next sequential blocks of memory relative to the most recent previous access in a page of memory.

Abstract: A cache for use in a memory controller, which processes data in a computer system having at least one processor, and a method for processing data utilizing a cache, are disclosed. The cache comprises a first array such as a tag array, a second array such as a data array, and a pointer for pointing to a portion of the second array that is associated with a portion of the first array, wherein the portion of the second array comprises the data to be processed, and wherein the number of times the at least one processor must undergo a first transfer latency is reduced. This is done by incorporating a prefetch mechanism within the cache. The computer system may include a plurality of processors with each data entry in the data array having an owner bit for each processor. The memory controller may also include a line preloader for prefetching data into the cache. Also, this design can be used in both single processor and multiprocessor systems.

Abstract: A method and system in a data processing system for dynamically scheduling the processing of a plurality of requests to access a disk, in which each of the plurality of requests is associated with a location on the disk, processes the requests in a first sequential order and determines the amount of time necessary to process a selected number of requests associated with locations between the current location on the disk and the most urgent request. At a time that is earlier than the deadline for processing the most urgent request by the amount of time necessary to process the selected number of requests, the method commences processing of the selected number of requests in a second sequential order.

Abstract: A method and system in data processing system are disclosed for efficiently servicing requests to access a disk. Each of the requests are associated with a location on the disk. The requests include real-time requests and non-real time requests. A most urgent one of the requests is determined. The most urgent one of the requests is associated with a first deadline and a first location on the disk. A second most urgent one of the requests is also determined. The second most urgent one of the requests is associated with a second deadline and a second location on the disk. The first deadline is earlier in time than the second deadline. A service time is determined. The service time is earlier in time than the first deadline. The service time is determined so that sufficient time will exist to service the most urgent one of the requests before the first deadline and service the second most urgent one of the requests before the second deadline.

Abstract: A method and system in data processing system are disclosed for the dynamic scheduling of a plurality of requests to access a disk. Each of the requests is associated with a location on the said disk which each of the requests is attempting to access. A scan queue is established for storing the plurality of requests. The plurality of requests are processed in a sequential order. The sequential order is determined utilizing the location on the disk being accessed by each of the requests. Upon one of the stored requests being urgent, the urgent request is processed. The urgent request is associated with a first location on said disk. Processing of the requests then continues in a second sequential order. The second sequential order is determined utilizing the first location. The next request to be processed is one of the requests which is associated with a physically closest location on the disk.

Abstract: Bus interface units interposed between a multiple processor bus and individually coupled to the respective processors in a complex incorporating a multitude of processors, where each bus interface unit includes block snoop control registers responsive to signals from a system memory controller including enhanced function supportive of I/O devices with and without block snooping compatibility. The BIU provides functionality for the bus of the multiple processors to be processor independent. This architecture reduces the number of snoop cycles which must access the processor bus, thereby effectively increasing the available processor bus bandwidth. This in turn effectively increases overall system performance.

Abstract: A method and system provide end-to-end flow control between a sender and a receiver attached to a network. The data is divided into a plurality of packets. A priority hierarchy of a plurality of priority levels is established. Each packet of data is associated with one of the priority levels. Transmission of the plurality of packets is initiated from a transmitter to a receiver transmitting the plurality of packets in the priority hierarchy. The real-time data is divided into a plurality of frames. Each of the plurality of frame is divided into multiple packets. Each of the plurality of frames is stored in a frame buffer included within the receiver. During transmission, a level of a plurality of frames included within the frame buffer is monitored. In response to the level crossing a first buffer threshold, a determination is made as to whether a first plurality of the multiple packets are associated with a first priority level.

Abstract: A mechanism is provided for supporting stack cache memory device management of POP read or PUSH write data in a computer system. The computer system further comprises a main memory and a processor associated with the stack cache memory device. The stack cache memory device includes at least one cache line having a plurality of address spaces arranged from a lowest address to a highest address. In response to the processor initiating a POP read or PUSH write operation, the mechanism provides logic for preventing placement of data in the cache which will not be reused by the processor, and for further preventing removal of data which may be reused by the processor.

Abstract: A memory controller having request queue and snoop tables is provided for functioning with bus interface units interposed between a multiple processor bus and individually coupled to the respective processors in a complex incorporating a multitude of processors, where each bus interface unit includes block snoop control registers responsive to signals from a system memory controller including enhanced function supportive of I/O devices with and without block snooping compatibility. The tables are compared to minimize and more efficiently institute snoop operations as a function of the presence or absence of the same listings in the tables. The BIU provides functionality for the bus of the multiple processors to be processor independent. This architecture reduces the number of snoop cycles which must access the processor bus, thereby effectively increasing the available processor bus bandwidth. This in turn effectively increases overall system performance.

Abstract: Bus interface units interposed between a multiple processor bus and individually coupled to the respective processors in a complex incorporating a multitude of processors, where each bus interface unit includes block snoop control registers responsive to signals from a system memory controller including enhanced function supportive of I/O devices with and without block snooping compatibility. The BIU provides functionality for the bus of the multiple processors to be processor independent. This architecture reduces the number of snoop cycles which must access the processor bus, thereby effectively increasing the available processor bus bandwidth. This in turn effectively increases overall system performance.

Abstract: A stack cache memory mechanism and method for managing the mechanism are provided. The mechanism comprises a data array including a plurality of storage elements in which stack data may be stored, and a plurality of individual stack tag sets for identifying beginning and ending locations of a corresponding plurality of individual stacks contained within the data array. Each of the individual stack tag sets comprise (i) a first register for containing an address in the data array corresponding to the top of a stack associated with that individual stack tag set and (ii) a second register for containing an address in the data array corresponding to the bottom of a stack associated with that individual stack tag set. A backward pointer array comprises a plurality of backward pointers which map each of the plurality of stack tag sets to address locations in the data array.

Abstract: An improved memory controller within a data processing system having a look-aside cache architecture is disclosed. The data processing system includes a processor having an upper level cache associated therewith, a memory controller having an associated controller memory, a processor bus coupled between the processor and the memory controller, and a main memory. The data processing system further includes a lower level cache coupled to the processor bus in parallel with the processor and memory controller. According to a first aspect of the present invention, the memory controller includes logic, which in response to receipt of a write request that will not be serviced by the lower level cache and for which the associated data is not a replaced modified cache line, stores the associated data within the controller memory associated with the memory controller, thereby optimizing data storage within the data processing system.

Abstract: A system for modeling computer instruction execution is disclosed. The public status register holds data representative of the status of the computer processing system. A combinational logic unit receives multibit data words from the public status register, as well as a source of program code. The combinational logic unit produces output data implementing a computer processor. A working status register, connected to the combinational logic unit, receives the combinational logic unit output signals. A clock signal generator, during first and second clock intervals, transfers the data from the working status register to the public status register only after all the combinational logic units have provided their output data for a given set of input data. A second clock interval will clock the public status register contents to the input of the combinational logic unit when a subsequent set of program code is presented to the combinational logic unit.