Abstract: A digital channel bank (11) has a plurality of channel units (17) interconnected to a digroup controller (10) over a shared data bus (30). A data processing circuit (FIG. 2) is included in each channel unit for the purpose of reducing the received signaling status information transmitted from each channel unit to the controller. The circuit (e.g., gates 24-27) serves to prevent single bit errors from being recognized as changes in the received signaling state. The circuit (gate 28) also insures that only changes in the signaling status, rather than current status, are reported to the controller. The circuit also incorporates a predetermined amount of delay for the purpose of eliminating multiple messages to the controller when the A and B path signaling bits change in adjacent signaling frames.

Abstract: The terminals in the frequency division multiplexed systems of the prior art employ many steps of modulation whose frequency variations, due to changes in the frequencies generated by the carrier oscillators, add to produce a frequency offset which is unacceptable in modern wideband systems. The terminals of the present invention use additional modulators connected to the carrier oscillators to reduce the frequency offset of the transmitted signal to the frequency variations of only a single oscillator.