Abstract: Two or more electronic devices are connected via a bus system, wherein one of the network devices controls other network devices. A first control application is uploaded from a first controlled device to the control device and a second control application is uploaded from a second controlled device into the first control application. The first and second controlled devices can be operated simultaneously using a single user interface shown on a display of the control device. The user interface of the first device is displayed as main user interface and the user interface of the second device is rendered within the main interface as reduced user interface, which includes only operation elements necessary for operation of the second device in combination with the first device. The generation of combined user interfaces is also possible when the second controlled device comprises features, which are not known at the production of the first controlled device.

Abstract: The invention concerns a solid state memory, comprising multiple logical units. The solid state memory contains an internal buffer for temporarily storing the incoming data steam before the incoming data are programmed to at least one page. The internal buffer keeps data that are not yet programmed in case a switch from one logical unit to another is performed. A method for operating such a device is presented.

Abstract: The present invention relates to a redundancy protected mass storage system with increased performance, and more specifically to a mass storage system with multiple storage units. According to the invention, the resources that are essentially provided for compensating the damage of one or more storage units are also used to enhance the system performance. For this purpose during reading or writing the storage system just waits for the responses of a minimum number of required storage units to start reading or writing, respectively.

Abstract: The present invention relates to a memory controller for an IC with an external DRAM, where the external DRAM has at least one memory bank and communicates with the IC via at least one channel. In line with the invention, the memory controller has a command scheduler which prioritizes the transmission of memory bank commands on the basis of a static priority allocation for commands and a dynamic priority allocation for channels.

Abstract: For writing, flash memory devices are physically accessed in a page-oriented mode, but such devices are not error-free in operation. According to the invention, when writing information data in a bus write cycle in a sequential manner into flash memory devices assigned to a common data bus, at least one of said flash memory devices is not fed for storage with a current section of said information data. In case an error is occurring while writing a current information data section into a page of a current one of said flash memory devices, said current information data section is written into a non-flash memory. During the following bus write cycle, while the flash memory device containing that defective page is normally idle, that idle time period is used for copying the corresponding stored section of said information data from said non-flash memory to a non-defect page of that flash memory device.

Abstract: Device for real-time streaming to an array of solid state memory device sets, said device comprising receiving means for receiving data from data streams of individual data rate in parallel, an input cache for buffering received data, a bus system for transferring data from the input buffer to the solid state memory device sets, and a controller adapted for using a page-receiving-time t_r, a page-writing-time wrt_tm, the data amount p and the individual data rates for dynamically controlling the bus system such that data received from the first data stream is transferred to solid state memory device sets comprised in a first subset of said array of solid state memory device sets, only, and data received from the at least a second data stream is transferred to solid state memory device sets comprised in a different second subset of said array of solid state memory device sets, only.

Abstract: For recording or replaying in real-time digital high bandwidth video signals, e.g. HDTV, HD progressive or HD film capture signals, very fast memories are required. For storage of streaming HD video data NAND FLASH memory based systems could be used. Flash memory devices are physically accessed in a page oriented mode. According to the invention, the input data are written in a multiplexed fashion into a matrix of multiple flash devices. A list processing is performed that is as simple and fast as possible, and defect pages of flash blocks of single flash devices are addressed within the matrix architecture. When writing in a sequential manner, the data content for the current flash device page of all flash devices of the matrix is copied to a corresponding storage area in an additional memory buffer. After the current series of pages has been written without error into the flash devices, the corresponding storage area in an additional memory buffer is enabled for overwriting with following page data.

Abstract: The present invention relates to a mass storage system with improved usage of buffer capacity, and more specifically to a mass storage system for real-time data storage with an embedded controller. According to the invention, the mass storage system has a first data path between a real-time data interface and a mass storage array, the first data path including a data buffer without access latency, and a second data path between an embedded processor and the mass storage array, wherein the data buffer without access latency is also used as a data buffer for non real-time data transfers between the embedded processor and the mass storage array.

Abstract: State of the art processor systems, esp. in embedded systems, are not able to process data under real-time conditions especially with throughput rates near 10 Gbps. So, when using interfaces like PCI Express (PCIe) or Infiniband or 10G-Ethernet for 10 Gbps data throughput, special data-paths have to process the high throughput rate data. But tasks like connection management or time uncritical control messaging are better manageable by a processor. According to the invention it is proposed a kind of multiplexer architecture that is needed to split between control and data-path access for a PCI Express based architecture.

Abstract: The present invention relates to a method for scheduling and controlling access to a multibank memory having at least two banks, and to an apparatus for reading from and/or writing to recording media using such method. According to the invention, the method comprises the steps of: writing an input stream to the first bank; switching the writing of the input stream to the second bank when a read command for the first bank is received; and switching the writing of the input stream back to the first bank when a read command for the second bank is received.

Abstract: For recording or replaying in real-time digital high bandwidth video signals, e.g. HDTV, HD progressive or HD film capture signals, very fast memories are required. For storage of streaming HD video data NAND FLASH memory based systems could be used. Flash memory devices are physically accessed in a page oriented mode. According to the invention, the input data are written in a multiplexed fashion into a matrix of multiple flash devices. A list processing is performed that is as simple and fast as possible, and defect pages of flash blocks of single flash devices are addressed within the matrix architecture. When writing in a sequential manner, the data content for the current flash device page of all flash devices of the matrix is copied to a corresponding storage area in an additional memory buffer. After the current series of pages has been written without error into the flash devices, the corresponding storage area in an additional memory buffer is enabled for overwriting with following page data.

Abstract: For recording or replaying in real-time digital HDTV signals very fast memories are required. For storage of streaming HD video data NAND flash memory based systems can be used. However, NAND flash memories have a slow write access, and they have unmasked production defects. Write or read operations can be carried out on complete physical data blocks only, and defect data blocks must not be used by the file system. Logical file system blocks are used which are larger than the physical data blocks. According to the invention the error reporting mechanism of the NAND flash memories is exploited. The video data is not only written to the non-volatile flash memories, but is also written to corresponding buffer slots (LFSB) of a volatile SRAM or DRAM memory operating in parallel. The video data are kept in the vola- tile memory until the flash memory holding the respective data has reported that its program or write operation succeeded.

Abstract: The invention relates to a method for synchronizing a transmitter memory area in a transmitter memory in a transmitter apparatus with a receiver memory area in a receiver memory in a receiver apparatus, and to a receiver apparatus. The transmitter memory area stores transmission data as transmission-data packets and the receiver memory area stores received data as received-data packets with associated error status data which respectively indicate an error status for the received-data packets. Before a reference identification is generated in the receiver apparatus, which, following transmission using a feedback message in the transmitter apparatus, is used for memory area synchronization, the error status data for a plurality of the received-data packets are checked in the receiver apparatus until a first received-data packet is ascertained for which the error status data indicate no error status.

Abstract: So-called LCH packets are defined in the Hiperlan Type 2 System for wire-free transmission of video and audio data streams. These LCH packets have a length of 54 data bytes. Furthermore, the Hiperlan/2 Standard provides for so-called ARQ messages to be sent back to the transmitter in an SCH packet in a QOS mode (Quality Of Service), in which all the LCH data packets must be confirmed by the receiver. Space for the LCH and SCH data packets must be provided in a buffer store in the Hiperlan/2 interface for each connection that is set up. When there is a possibility of several hundred connections having been set up, separate reservation of memory areas for LCH and SCH packets would involve considerable complexity for the memory organization. The invention proposes that only one common area be reserved for LCH and SCH packets in the buffer store. The section which is provided for each LCH package is of such a size that it corresponds to a value 2n where n?[0, 1, 2, 3, . . .

Abstract: The present invention relates to a method and a device for the fast verification of sector addresses in a data stream obtained from a recording medium upon a request from a microcontroller. According to the invention, the method comprises the steps of: reading the data stream from the recording medium; decoding the data stream to obtain a decoded data stream comprising user data and sector addresses; comparing the sector addresses with a range of valid sector addresses; and transmitting only user data having sector addresses within the range of valid sector addresses; whereby dedicated comparing means are provided for performing the comparing step independently of the microcontroller.

Abstract: The present invention relates to a memory controller for an IC with an external DRAM, where the external DRAM has at least one memory bank and communicates with the IC via at least one channel. In line with the invention, the memory controller has a command scheduler which prioritizes the transmission of memory bank commands on the basis of a static priority allocation for commands and a dynamic priority allocation for channels.

Abstract: Real time streaming over serial buses busing Internet protocol IP is becoming more and more important. With new bus technologies e.g. 10 Gbit Ethernet even streaming in HD cinematography quality and uncompressed form becomes possible. In this case, however, data access management by software means is critical or simply not possible for performance reasons even if high performance micro-controllers are used where the software runs. The invention proposes for an apparatus in a network to implement hardware means for processing the real-time critical data packets as well as software means for processing the real-time uncritical data packets and a filter algorithm respectively a de-multiplexer for analyzing packet header and passing the real-time critical data packets to the hardware means and the real-time uncritical data packets to the software means.

Abstract: The invention relates to a method for synchronizing a transmitter memory area in a transmitter memory in a transmitter apparatus with a receiver memory area in a receiver memory in a receiver apparatus, and to a receiver apparatus. The transmitter memory area stores transmission data as transmission-data packets and the receiver memory area stores received data as received-data packets with associated error status data which respectively indicate an error status for the received-data packets. Before a reference identification is generated in the receiver apparatus, which, following transmission using a feedback message in the transmitter apparatus, is used for memory area synchronization, the error status data for a plurality of the received-data packets are checked in the receiver apparatus until a first received-data packet is ascertained for which the error status data indicate no error status.

Abstract: The present invention relates to a method for scheduling and controlling access to a multibank memory having at least two banks, and to an apparatus for reading from and/or writing to recording media using such method. According to the invention, the method comprises the steps of: writing an input stream to the first bank; switching the writing of the input stream to the second bank when a read command for the first bank is received; and switching the writing of the input stream back to the first bank when a read command for the second bank is received.

Abstract: Method for fast verification of sector addresses The present invention relates to a method and a device for the fast verification of sector addresses (9) in a data stream (2) obtained from a recording medium (1) upon a request from a microcontroller (13). According to the invention, the method comprises the steps of: reading the data stream (2) from the recording medium (1); decoding the data stream (2) to obtain a decoded data stream comprising user data (6) and sector addresses (9); comparing the sector addresses (9) with a range (12) of valid sector addresses; and transmitting only user data (8) having sector addresses (9) within the range (12) of valid sector addresses; whereby dedicated comparing means (10) are provided for performing the comparing step independently of the microcontroller (13).