Abstract: In one embodiment, a method implemented in a microprocessor, including receiving a fetched branch instruction; performing a privilege level test on a fetched branch instruction using a privilege level indicated by a first tag corresponding to a privilege level in a branch prediction table comprising plural entries, each of the plural entries comprising a tag corresponding to a privilege level; and providing a prediction branch miss for the fetched branch instruction based on a failure of the privilege level test.

Abstract: In one embodiment, a branch prediction control system is configured to move a mispredicted conditional branch from a smaller cache side that uses the lower complexity conditional branch predictor to one of the two large cache sides that uses the higher complexity conditional branch predictors. The move (write) is achieved according to a configurable probability or chance to escape misprediction recurrence and results in a reduced amount of mispredictions for the given branch instruction.

Abstract: In one embodiment, a microprocessor, comprising: first logic configured to dynamically adjust a maximum prefetch count based on a total count of predicted taken branches over a predetermined quantity of cache lines; and second logic configured to prefetch instructions based on the adjusted maximum prefetch count.

Abstract: In one embodiment, a microprocessor, comprising: a branch prediction table comprising plural entries, wherein at least a portion of the plural entries corresponds to an indirect branch type; and an indirect valid table; wherein based on an indirect branch instruction fetch, an entry corresponding to an indirect branch instruction in the branch prediction table is configured as invalid based on clearing a corresponding entry in the indirect valid table.

Abstract: In one embodiment, a branch processing method comprising receiving information from at least two branch execution units; writing two updates per clock cycle to respective first and second write queues based on the information; and writing from the first write queue up to two updates per clock cycle into plural tables of a first predictor and a single update for the single clock cycle when there is an expected write collision, the first predictor comprising a single write or read/write port.

Abstract: In one embodiment, a branch processing method, comprising: assigning plural branch instructions for a given clock cycle to primary branch information and secondary branch information; routing the primary branch information along a first path having adder logic and the secondary branch information along a second path having no adder logic; and writing the primary branch information including a displacement branch target address to a branch order table (BOT) and the secondary branch information without a target address to the BOT.

Abstract: In one embodiment, a microprocessor, comprising: an instruction cache configured to receive an instruction fetch comprising a first byte portion and a second byte portion; a side cache tag array configured to signal further processing of the second byte portion in addition to the first byte portion based on a hit of the side cache tag array; and a side cache data array configured to store instruction data for the second byte portion.

Abstract: In one embodiment, a microprocessor, comprising: a branch prediction table comprising plural entries, wherein at least a portion of the plural entries corresponds to an indirect branch type; and an indirect valid table; wherein based on an indirect branch instruction fetch, an entry corresponding to an indirect branch instruction in the branch prediction table is configured as invalid based on clearing a corresponding entry in the indirect valid table.

Abstract: In one embodiment, a method implemented in a microprocessor, the method comprising: receiving a fetched branch instruction; performing a privilege level test on a fetched branch instruction using a privilege level indicated by a first tag corresponding to a privilege level in a branch prediction table comprising plural entries, each of the plural entries comprising a tag corresponding to a privilege level; and providing a prediction branch miss for the fetched branch instruction based on a failure of the privilege level test.

Abstract: In one embodiment, a microprocessor, comprising: an instruction cache configured to receive an instruction fetch comprising a first byte portion and a second byte portion; a side cache tag array configured to signal further processing of the second byte portion in addition to the first byte portion based on a hit of the side cache tag array; and a side cache data array configured to store instruction data for the second byte portion.

Abstract: In one embodiment, a branch prediction control system is configured to move a mispredicted conditional branch from a smaller cache side that uses the lower complexity conditional branch predictor to one of the two large cache sides that uses the higher complexity conditional branch predictors. The move (write) is achieved according to a configurable probability or chance to escape misprediction recurrence and results in a reduced amount of mispredictions for the given branch instruction.

Abstract: In one embodiment, a microprocessor, comprising: first logic configured to dynamically adjust a maximum prefetch count based on a total count of predicted taken branches over a predetermined quantity of cache lines; and second logic configured to prefetch instructions based on the adjusted maximum prefetch count.

Abstract: In one embodiment, a branch processing method comprising receiving information from at least two branch execution units; writing two updates per clock cycle to respective first and second write queues based on the information; and writing from the first write queue up to two updates per clock cycle into plural tables of a first predictor and a single update for the single clock cycle when there is an expected write collision, the first predictor comprising a single write or read/write port.

Abstract: In one embodiment, a branch processing method, comprising: assigning plural branch instructions for a given clock cycle to primary branch information and secondary branch information; routing the primary branch information along a first path having adder logic and the secondary branch information along a second path having no adder logic; and writing the primary branch information including a displacement branch target address to a branch order table (BOT) and the secondary branch information without a target address to the BOT.

Abstract: In one embodiment, a microprocessor, comprising: an instruction cache comprising programming instructions at a plurality of cache addresses; a quick predictor configured to receive information associated with a first branch instruction corresponding to a first cache address of the instruction cache and, based on a match at the quick predictor, provide a first branch prediction during a first stage; and a branch target address cache (BTAC) operating according to a second set of stages subsequent to the first stage, the BTAC configured to receive the information associated with the first branch instruction and determine a second branch prediction, the BTAC configured to override the first branch prediction and update the quick predictor by writing a branch target address associated with the second branch prediction to the quick predictor at a time corresponding to the second set of stages.

Abstract: In one embodiment, a microprocessor, comprising: prediction logic comprising a branch predictor comprising a group of multi-set associative tables, each of the tables corresponding to branch pattern histories of different lengths; and control logic configured to provide an adjustable write policy for the prediction logic.

Abstract: In one embodiment, a microprocessor, comprising: first logic configured to detect that a fetched cache address matches at least one of two previous cache addresses; and second logic configured to adjust a branch pattern used for conditional branch prediction based on the match and combine the cache address with the adjusted branch pattern to form a conditional branch predictor address.

Abstract: In a microprocessor that has an instruction set architecture in which the instructions may include a variable number of prefix bytes, an apparatus for efficiently extracting instructions from a stream of undifferentiated instruction bytes. Decode logic determines which byte is an opcode byte for each instruction of a plurality of instructions within the stream of undifferentiated instruction bytes. The opcode byte is the first non-prefix byte of the instruction. The decode logic accumulates prefix information onto the opcode byte of the instruction for each instruction of the plurality of instructions. A queue holds the stream of undifferentiated instruction bytes and the accumulated prefix information. Extraction logic extracts the plurality of instructions from the queue in one clock cycle independent of the number of prefix bytes included in each of the plurality of instructions.

Abstract: A microprocessor includes a branch target address cache (BTAC), each entry thereof configured to store branch prediction information for at most N branch instructions. An execution unit executes a branch instruction previously fetched in a fetch quantum. Update logic determines whether the BTAC is already storing information for N branch instructions within the fetch quantum (N is at least two), updates the BTAC for the branch instruction if the BTAC is not already storing information for N branch instructions, determines whether a type of the branch instruction has a higher replacement priority than a type of the N branch instructions if the BTAC is already storing information for N branch instructions, and updates the BTAC for the branch instruction if the type of the branch instruction has a higher replacement priority than the type of the N branch instructions already stored in the BTAC.

Abstract: An apparatus in a microprocessor that has an instruction set architecture in which instructions may include a length-modifying prefix used to select an address/operand size other than a default address/operand size, wherein the apparatus marks the start byte and the end byte of each instruction in a stream of instruction bytes. Decode logic decodes each instruction byte of a predetermined number of instruction bytes to determine whether the instruction byte specifies a length-modifying prefix and generates a start mark and an end mark for each of the instruction bytes based on an address/operand size. Operand/address size logic provides the default operand/address size to the decode logic to use to generate the start and end marks during a first clock cycle during which the decode logic decodes the predetermined number of instruction bytes.