Abstract: A method for compressing speech. An audio signal comprising speech is broken down into its phonetic components. These phonetic components are then converted into data elements that represent each of the phonetic components. The determination of data elements is accomplished using a predefined table that correlates phonetic sounds to data elements. The data elements representing the phonetic sounds are then stored.

Abstract: A processor including a first execution core section clocked to perform execution operations at a first clock frequency, and a second execution core section clocked to perform execution operations at a second clock frequency which is different than the first clock frequency. The second execution core section runs faster and includes a data cache and critical ALU functions, while the first execution core section includes latency-tolerant functions such as instruction fetch and decode units and non-critical ALU functions. The processor may further include an I/O ring which may be still slower than the first execution core section. Optionally, the first execution core section may include a third execution core section whose clock rate is between that of the first and second execution core sections. Clock multipliers/dividers may be used between the various sections to derive their clocks from a single source, such as the I/O clock.

Abstract: A method for compressing music into a digital format. An audio signal that corresponds to music is received and converted from an analog signal to a digital signal. The audio signal is analyzed, and a tone is identified. The musical note and instrument that correspond to the tone are determined, and data elements that represent the musical note and instrument are then stored.

Abstract: A clocking scheme provides for an improved latching of an output from a domino circuit by delaying a precharging of a domino node. The precharging delay is achieved by introducing the delay in the clocking circuitry which activates the precharging of the domino node. No delay is introduced in the data path in order not to delay the evaluation and transmission of the data signal. During one phase of a clocking cycle, the domino node is precharged to a predetermined logic state. Also during this precharge phase, an input latch couples an input data signal to the domino circuit. During the other phase of the clocking cycle, the domino circuit performs a logic operation based on the input signal. Also during this evaluation phase, an output latch latches the logic state of the domino output for transmission from the output latch.

Abstract: High speed and high drive BiCMOS buffers, inverters, and gates receiving synchronous differential inputs are provided having at least two npn bipolar transistors and at least one nMOS transistor. The first bipolar transistor has a base receiving a noninverting input, a collector coupled to the high voltage rail, and an emitter coupled to the circuit output. In several embodiments, the second bipolar transistor has its collector coupled to the emitter of the first bipolar transistor, its emitter coupled to ground, and its base coupled to the source of an nMOS transistor which is receiving the inverting input at its gate. In these embodiments, the output is taken from the emitter of the first bipolar transistor and the collector of the second bipolar transistor with the first bipolar transistor pulling up when the input is high, and the second bipolar transistor pulling down when the input is low.

Abstract: In a driver circuit, high- and low-impedance drive means (26 and 28 respectively) operate in parallel to effect a desired output transition. Adaptive control means 32 respond to a threshold value of the output signal (VO) and turn off the low-impedance drive means in the course of the output transition. The low initial output impedance of the driver circuit effects rapid charging of a line capacitance CL, while toward the end of the output transition the higher output impedance of the driver circuit more closely matches the input impedance ZL of a load circuit. This higher impedance dampens ringing and thereby reduces induced supply line noise which is conventionally associated with high-speed driver circuits.

Abstract: A circuit employable as a differential multiplexer (10, 310, or 610) or as a differential logic gate (110, 210, 250, 410, or 510) of either the OR/NOR or EXCLUSIVE OR/EXCLUSIVE NOR type contains four pass gates that operate on four circuit input signals and are controlled by two additional circuit input signals. Two of the pass gates drive a bipolar transistor serially coupled to a first FET driven from the other two pass gates. Likewise, the second pair of pass gates drive another bipolar transistor serially coupled to another FET driven from the first pair of pass gates. The bipolar transistors supply respective circuit output signals. The two FETs are of a first polarity. The circuit preferably includes a pair of FETs of a second polarity opposite to the first polarity. The second pair of FETs are arranged so as to provide output pull-up/pull-down assistance for the bipolar transistors.

Abstract: The driver circuit comprises drive means (Q2) for drawing an output current from a bus line (13) in a first state of the circuit. An output diode (S1) in the path of the output current is reverse biased in a second state of the circuit to isolate the drive means from the bus line. A control current (I.sub.Q2B) for the drive transistor is drawn from the bus line (13), beyond the output diode (S1). By this means, power dissipation (heat) within the driver circuit due to the control current is eliminated. The driver circuit also comprises means (26, S3, P1) for biasing the output during connection of the circuit to a live bus line, so as to reduce noise for other circuits connected to the bus line.

Abstract: An edge-sensitive dynamic switch center around a transmission gate (16) formed with a pair of complementary FET's (Q.sub.N and Q.sub.P) coupled together in parallel between a pair of nodes (1 and 2). The signals at the two nodes vary between a low voltage level and a high voltage level. An inverter (17) is coupled between the gate electrodes of the FET's. A delay element (18) is coupled between one of the nodes and one of the gate electrodes. Due to the transmission delays through the delay element and the inverter, the switch turns off with a controlled delay.

Abstract: A voltage translator containing a bipolar transistor (Q1), a rectifier (10), a resistor (R1), and a first clamp (12) converts an input voltage (V.sub.I) into one or more output voltages of restricted voltage swing. The first clamp clamps the emitter voltage of the transistor when it is turned on. In one version, the translator includes a second clamp (14) that clamps the collector voltage of the translator when it is turned off. The translator then provides an output voltage (V.sub.O) inverse to the input voltage. In another version, the first clamp is connected between a voltage supply (V.sub.EE) and the emitter of the transistor. Its collector is connected directly to another voltage supply (V.sub.CC) so that the translator only makes non-inverting translations.

Abstract: A switching device (22) responsive to an input voltage V.sub.A is powered by low and high internal supply voltages V.sub.L and V.sub.H. The device changes state as V.sub.A -V.sub.L passes a threshold voltage V.sub.T. After the device makes a desired change of state in response to rising V.sub.A, a hysteresis circuit (24) temporarily decreases V.sub.T below that which would otherwise be present. Likewise, after the device makes a desired change of state in the opposite direction when V.sub.A is falling, the hysteresis circuit temporarily decreases V.sub.T. In both cases, V.sub.T later automatically returns to its original value. This dynamic hysteresis prevents spikes in V.sub.L and V.sub.H from causing undesired changes in state.

Abstract: A bipolar signal translator contains a pair of transistors (Q1 and Q2) arranged as a current mirror with their emitters coupled to a voltage supply (V.sub.EE) by way of a pair of impedance elements (R4 and R5) that improve stability. Their collectors are coupled through another pair of impedance elements (R1 and R2) to an input transistor (Q4 or Q5) and to a device circuit (D1 and D2, D3 and D4, or Q4). The collector of one of the current-mirror transistors (Q2) is coupled to the base of an output transistor (Q3) whose collector is preferably coupled through an output impedance element (R3) to a current-control transistor (Q6) that improves power utilization.

Abstract: A TTL circuit having a pair of current sources (R2/V.sub.CC and R2/V.sub.CC) and a pair of transistors (Q1 and Q2) arranged in a standard TTL input/inverting configuration has hysteresis at the input signal (V.sub.X) for providing noise protection. A hysteresis circuit (10) suitably containing another current source (R3/V.sub.CC) coupled to the base of the inverting transistor (Q2) and a rectifier (12) coupled between the collector of the inverting transistor and the current source (R1/V.sub.CC) coupled to the base of the input transistor (Q1) provides the hysteresis at the circuit switching points.

Abstract: A logic circuit in which (1) a first bipolar transistor has a base, an emitter, and a collector coupled to a voltage/current source, and (2) a second bipolar transistor has a base coupled to the emitter of the first transistor, an emitter coupled to a constant voltage source, and a collector coupled to the voltage/current source contains operational control circuitry for preventing the second transistor from either turning off or normally going into deep saturation. Each transistor is typically an NPN device. The operational control circuitry may then comprise (1) first circuitry for providing current from the voltage/current source in a single current-flow direction to the collector of the second transistor and (2) second circuitry for providing current from the first circuitry in a single current-flow direction to the base of the second transistor. Optimally, the first circuitry prevents the second transistor from ever going into deep saturation.