Abstract: A multiprocessor system that assures forward progress of local processor requests for data by preventing other nodes from accessing the data until the processor request is satisfied. In one aspect of the invention, the local processor requests data through a remote cache interconnect. The remote cache interconnect tells the local processor to retry its request for data at a later time, so that the remote cache interconnect has sufficient time to obtain the data from the system interconnect. When the remote cache interconnect receives the data from the system interconnect, a hold flag is set. Any requests from other nodes for the data are rejected while the hold flag is set. When the local processor issues a retry request, the data is delivered to the processor and the hold flag is cleared. Other nodes may then obtain control of the data.

Abstract: A method and apparatus for maintaining processor consistency in a multiprocessor computer such as a multinode computer system are disclosed. A processor proceeds with write operations before its previous write operations complete, while processor consistency is maintained. A write operation begins with a request by the processor to invalidate copies of the data stored in other nodes. This current invalidate request is queued while acknowledging to the processor that the request is complete even though it has not actually completed. The processor proceeds to complete the write operation by changing the data. It can then execute subsequent operations, including other write operations. The queued request, however, is not transmitted to other nodes in the computer until all previous invalidate requests by the processor are complete. This ensures that the current invalidate request will not pass a previous invalidate request.

Abstract: Local memory on a node in a multinode, multiprocessor computer system with distributed shared memory and a remote cache is efficiently updated through the use of a combined tag stored in a tag cache. In response to a local processor request for access to local memory that does not contain a current copy of the data requested, a combined tag is formed from a memory tag and a remote cache tag. The combined tag allows the node to operate in accordance with the network protocol such as the Scalable Coherent Interface (SCI) while the memory is being updated, acting as memory in response to requests from other nodes to the memory and as a cache in response to requests from other nodes to the remote cache. In this way the memory is updated quickly and the remote cache is not required to store data that is better stored in the local memory.

Abstract: In order that a microprocessor can respond properly to both instruction words and data words that are organized in off-chip memory in accordance with either of two byte order conventions, on-chip circuitry is added which controllably changes the byte order of both the instructions and the data to that of the microprocessor.