Abstract: A memory programming circuit for programming a non-volatile memory device having an array structure includes a plurality of rows, each row having a row index and comprising one or more memory units, each memory unit being configured to receive one or more input signals and to deliver one or more output signals, the memory programming circuit comprising: a first source line connected to the top electrode of the memory units comprised at rows of odd row indices, and a second source line connected to the top electrodes of the memory units comprised at rows of even row indices.

Abstract: The present invention concerns a method for programming a Bayesian neural network (BNN) in a RRAM memory. After the BNN has been trained on a dataset D, the joint posterior probability distribution of the synaptic coefficients, p(w|D) is decomposed into a mixture of multivariate mean-field Gaussian components by GMM. The weighting coefficients and the parameters of these multivariate Gaussian components are estimated by MDEM (Multi-Dimensional Expectation Maximization) with two constraints. According to the first constraint, the off-diagonal terms of the covariance matrix of each component are forced to zero. According to the second constraint, the couples of mean values and diagonal terms of the covariance matrix of each component are constrained to belong to a hardware compliance domain determined by a relationship between the conductance mean value and conductance standard deviation of a memristor programmed by a SET or RESET operation.

Abstract: The present disclosure relates to a synapse circuit (202) for a Bayesian neural network, the synapse circuit comprising: a first resistive memory device (302) coupling a first voltage rail (Vread) to a first terminal of a capacitor (308), the first terminal of the capacitor (308) being coupled to a second voltage rail via a variable conductance (306); and a second resistive memory device (304) coupling a second voltage rail (Vdata) to an output line (312) of the synapse circuit (202), wherein a second terminal of the capacitor (306) is coupled to a terminal of the second resistive memory device (304).

Abstract: The present disclosure relates to a synapse circuit of a neural network for performing TD-lambda temporal difference learning, the neural network approximating a value function, the synapse circuit comprising: a first resistive memory device (506); a second resistive memory device (516); and a synapse control circuit (528) configured to update a synaptic weight (g?) of the synapse circuit by programming a resistive state of the first resistive memory device (506) based on a programmed conductance of the second resistive memory device (516).

Abstract: A memory programming circuit for programming a non-volatile memory device having an array structure includes a plurality of rows, each row having a row index and comprising one or more memory units, each memory unit being configured to receive one or more input signals and to deliver one or more output signals, the memory programming circuit comprising: a first source line connected to the top electrode of the memory units comprised at rows of odd row indices, and a second source line connected to the top electrodes of the memory units comprised at rows of even row indices.

Abstract: The present disclosure relates to a neuron circuit of a spiking neural network comprising: a first resistive switching memory device having a conductance that decays over time; and a programming circuit configured to reset the resistive state of the first resistive switching element in response to a spike in an output voltage of the neuron circuit.

Abstract: The present disclosure relates to a synapse circuit of a spiking neural network comprising: at least one resistive switching memory device having a conductance that decays over time; and at least one programming circuit configured to store an eligibility trace by programming a resistive state of the at least one resistive memory device.

Abstract: A Bayesian neural network including an input layer, and, an output layer, and, possibly, one or more hidden layer(s). Each neuron of a layer is connected at its input with a plurality of synapses, the synapses of the plurality being implemented as a RRAM array constituted of cells, each column of the array being associated with a synapse and each row of the array being associated with an instance of the set of synaptic coefficients, the cells of a row of the RRAM being programmed during a SET operation with respective programming current intensities, the programming intensity of a cell being derived from the median value of a Gaussian component obtained by GMM decomposition into Gaussian components of the marginal posterior probability of the corresponding synaptic coefficient, once the BNN model has been trained on a training dataset.

Abstract: The present disclosure relates to a routing circuit for routing signals between neuron circuits of an artificial neural network, the routing circuit comprising: a first memory cell (302) having an input coupled to a first input line (304) of the routing circuit and an output coupled to a first column line (308); a second memory cell (302) having an input coupled to a second input line (304) of the routing circuit and an output coupled to the first column line (308); and a first comparator circuit (310) configured to compare a signal (IREAD1) on the first column line (308) with a reference level, and to selectively assert a signal (VOUT1) on a first output line (312) of the routing circuit based on the comparison.

Abstract: A method for training a logistic regression classifier on a dataset by using a resistive RAM as hardware accelerator, each row of the resistive RAM including cells which can be programmed in a first resistance state or a second resistance state. The probability of a data element belonging to a class is modelled by a logistic function applied to a score of the element, where is a parameter vector of the model. The logistic regression classifier is trained by populating the resistive RAM with samples of a model parameter vector which are obtained by MCMC sampling. Once populated, the resistive RAM can be used for classifying new data.

Abstract: A programmable artificial neuron emitting an output signal controlled by at least one control parameter, includes, for each control parameter, a capacitor and at least one block including at least one multiplexer configured to be in two states: a programming state and an operating state; a transistor; and a non-volatile resistive random access memory connected in series with the transistor, the capacitor and the resistive random access memory being mounted in parallel. The multiplexer is configured to, when it is in the programming state, set a resistance value of the resistive random access memory to set the value of the control parameter; when it is in the operating state, conserve the set resistance value of the resistive random access memory.

Abstract: A programmable artificial neuron emitting an output signal controlled by at least one control parameter, includes, for each control parameter, a capacitor and at least one block including at least one multiplexer configured to be in two states: a programming state and an operating state; a transistor; and a non-volatile resistive random access memory connected in series with the transistor, the capacitor and the resistive random access memory being mounted in parallel. The multiplexer is configured to, when it is in the programming state, set a resistance value of the resistive random access memory to set the value of the control parameter; when it is in the operating state, conserve the set resistance value of the resistive random access memory.