Patents by Inventor Thomas Dyer Bonifield

Thomas Dyer Bonifield has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • High voltage hybrid polymeric-ceramic dielectric capacitor
    Patent number: 8890223
    Abstract: An integrated circuit includes isolation capacitors which include a silicon dioxide dielectric layer and a polymer dielectric layer over the layer of silicon dioxide. The silicon dioxide dielectric layer and the polymer dielectric layer extend across the integrated circuit. Top plates of the isolation capacitors have bond pads for wire bonds or bump bonds. Bottom plates of the isolation capacitors are connected to components of the integrated circuit. Other bond pads are connected to components in the integrated circuit through vias through the silicon dioxide dielectric layer and the polymer dielectric layer.
    Type: Grant
    Filed: August 6, 2013
    Date of Patent: November 18, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Thomas Dyer Bonifield, Byron Williams, Shrinivasan Jaganathan
  • Double wafer carrier process for creating integrated circuit die with through-silicon vias and micro-electro-mechanical systems protected by a hermetic cavity created at the wafer level
    Patent number: 7960840
    Abstract: A TSV-MEMS packaging process is provided. The process includes forming TSVs in the front side of the product wafer, and attaching a first carrier to the front side of the product wafer, subsequent to forming TSVs. The process further includes thinning the back side of the product wafer to expose TSV tips, detaching the first carrier from the front side of the product wafer, and transferring the thinned wafer to a second carrier with back side adhered to the second wafer carrier. Semiconductor components are added to the front side of the product wafer, followed by forming a hermetic cavity over the added semiconductor components, and detaching the second carrier from the back side of the product wafer. Wafer level processing continues after detaching the second carrier.
    Type: Grant
    Filed: May 11, 2009
    Date of Patent: June 14, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Thomas Dyer Bonifield, Thomas W. Winter, William R. Morrison, Gregory D. Winterton, Asad M. Haider
  • DOUBLE WAFER CARRIER PROCESS FOR CREATING INTEGRATED CIRCUIT DIE WITH THROUGH-SILICON VIAS AND MICRO-ELECTRO-MECHANICAL SYSTEMS PROTECTED BY A HERMETIC CAVITY CREATED AT THE WAFER LEVEL
    Publication number: 20090280602
    Abstract: A TSV-MEMS packaging process is provided. The process includes forming TSVs in the front side of the product wafer, and attaching a first carrier to the front side of the product wafer, subsequent to forming TSVs. The process further includes thinning the back side of the product wafer to expose TSV tips, detaching the first carrier from the front side of the product wafer, and transferring the thinned wafer to a second carrier with back side adhered to the second wafer carrier. Semiconductor components are added to the front side of the product wafer, followed by forming a hermetic cavity over the added semiconductor components, and detaching the second carrier from the back side of the product wafer. Wafer level processing continues after detaching the second carrier.
    Type: Application
    Filed: May 11, 2009
    Publication date: November 12, 2009
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Thomas Dyer BONIFIELD, Thomas W. WINTER, William R. MORRISON, Gregory D. WINTERTON, Asad M. HAIDER