Abstract: A fixture assembly and method of forming a chip assembly is provided. The fixture assembly includes a first plate having an opening sized to accommodate a chip mounted on a laminate. The fixture assembly further includes a second plate mated to the first plate by at least one mechanical fastening mechanism. The fixture assembly further includes a space defined by facing surfaces of the first plate and the second plate and confined by a raised stepped portion of at least one of the first plate and the second plate. The space is coincident with the opening. The space is sized and shaped such that the laminate is confined within the space and directly abuts the stepped portion and the facing surfaces of the first plate and the second plate to be confined in X, Y and Z directions.

Abstract: A fixture for shaping a laminate substrate includes a trap ring, a base plate and a center button. The base plate includes a recess adapted to receive the laminate substrate. The center button is disposed in an opening in the base plate. The center button may be adjusted to shape the laminate substrate.

Abstract: A method including providing a fixture comprising a trap ring, a base plate having a recess adapted to receive a laminate substrate, the base plate including an opening and an adjustable height center button disposed in the opening, the opening being located within the recess and located in a center of the laminate substrate, characterizing the laminate substrate for warpage characteristics by using one of room temperature techniques and elevated temperature techniques, determining a horizontal plane distortion based on the warpage characteristics, and placing the laminate substrate into the fixture with an adjustment to correct the horizontal plane distortion, the adjustment is provided by the adjustable height center button, wherein the adjustable height center button contacts the laminate substrate. The method further includes fluxing the laminate substrate, placing a chip onto the laminate substrate, and placing the fixture into a reflow furnace to join the chip and the laminate substrate.

Abstract: A method including providing a laminate substrate, characterizing the laminate substrate for warpage characteristics, determining a horizontal plane distortion based on the warpage characteristics, and placing the laminate substrate into a fixture with an adjustment to correct the horizontal plane distortion, the adjustment being located in a center of the laminate substrate, wherein the adjustment contacts the laminate substrate. The method may further include fluxing the laminate substrate, placing a chip onto the laminate substrate, and placing the fixture into a reflow furnace to join the chip and the laminate substrate.

Abstract: A fixture assembly and method of forming a chip assembly is provided. The fixture assembly includes a first plate having an opening sized to accommodate a chip mounted on a laminate. The fixture assembly further includes a second plate mated to the first plate by at least one mechanical fastening mechanism. The fixture assembly further includes a space defined by facing surfaces of the first plate and the second plate and confined by a raised stepped portion of at least one of the first plate and the second plate. The space is coincident with the opening. The space is sized and shaped such that the laminate is confined within the space and directly abuts the stepped portion and the facing surfaces of the first plate and the second plate to be confined in X, Y and Z directions.

Abstract: A fixture assembly and method of forming a chip assembly is provided. The fixture assembly includes a first plate having an opening sized to accommodate a chip mounted on a laminate. The fixture assembly further includes a second plate mated to the first plate by at least one mechanical fastening mechanism. The fixture assembly further includes a space defined by facing surfaces of the first plate and the second plate and confined by a raised stepped portion of at least one of the first plate and the second plate. The space is coincident with the opening. The space is sized and shaped such that the laminate is confined within the space and directly abuts the stepped portion and the facing surfaces of the first plate and the second plate to be confined in X, Y and Z directions.

Abstract: A method for shaping a laminate substrate includes characterizing the laminate substrate for warpage characteristics. The laminate substrate is placed into a fixture with a correction to shape the laminate substrate based on the warpage characteristics. The laminate substrate is fluxed. A chip is placed onto the laminate substrate. The fixture is placed into a reflow furnace to join the chip and the laminate substrate. The fixture is removed from the reflow furnace. A warpage measurement is performed on the joined chip and laminate substrate. The correction may be modified if shorts are observed at the chip site.

Abstract: A fixture for shaping a laminate substrate includes a trap ring, a base plate and a center button. The base plate includes a recess adapted to receive the laminate substrate. The center button is disposed in an opening in the base plate. The center button may be adjusted to shape the laminate substrate.

Abstract: A method of fabricating a chip package is provided. The chip package includes a laminate, a chip and conductive elements interposed between the chip and the laminate by which signals are transmitted among the chip and the laminate. The method includes dispensing a first underfill in a space defined between opposing faces of the chip and the laminate and dispensing a second underfill at least at a portion of an edge of the chip, the second underfill including a high aspect ratio material.

Abstract: A system and method comprises depositing a dielectric layer on a substrate and depositing a metal layer on the dielectric layer. The system and method further includes depositing a high temperature diffusion barrier metal cap on the metal layer. The system and method further includes depositing a second dielectric layer on the high temperature diffusion barrier metal cap and the first dielectric layer, and etching a via into the second dielectric layer, such that the high temperature diffusion barrier metal cap is exposed. The system and method further includes depositing an under bump metallurgy in the via, and forming a C4 ball on the under bump metallurgy layer.

Abstract: An apparatus, system, and method are disclosed for connecting an integrated circuit device to a substrate. A plurality of standard diameter pillars and three or more increased diameter pillars are disposed on an integrated circuit device. The increased diameter pillars have a diameter that is greater than the standard diameter pillars and a height that is similar to the standard diameter pillars. The standard diameter pillars and the increased diameter pillars form a pattern on the integrated circuit device that corresponds to contact pads on a substrate opposite the integrated circuit device. A first group of solder bumps is disposed between the standard diameter pillars and the contact pads. A second group of solder bumps is disposed between the increased diameter pillars and the contact pads. The second group of solder bumps has pre-connection heights that are greater than pre-connection heights of the first group of solder bumps.

Abstract: A fixture assembly and method of forming a chip assembly is provided. The fixture assembly includes a first plate having an opening sized to accommodate a chip mounted on a laminate. The fixture assembly further includes a second plate mated to the first plate by at least one mechanical fastening mechanism. The fixture assembly further includes a space defined by facing surfaces of the first plate and the second plate and confined by a raised stepped portion of at least one of the first plate and the second plate. The space is coincident with the opening. The space is sized and shaped such that the laminate is confined within the space and directly abuts the stepped portion and the facing surfaces of the first plate and the second plate to be confined in X, Y and Z directions.

Abstract: A fixture assembly and method of forming a chip assembly is provided. The fixture assembly includes a first plate having an opening sized to accommodate a chip mounted on a laminate. The fixture assembly further includes a second plate mated to the first plate by at least one mechanical fastening mechanism. The fixture assembly further includes a space defined by facing surfaces of the first plate and the second plate and confined by a raised stepped portion of at least one of the first plate and the second plate. The space is coincident with the opening. The space is sized and shaped such that the laminate is confined within the space and directly abuts the stepped portion and the facing surfaces of the first plate and the second plate to be confined in X, Y and Z directions.

Abstract: A method of fabricating a chip package is provided. The chip package includes a laminate, a chip and conductive elements interposed between the chip and the laminate by which signals are transmitted among the chip and the laminate. The method includes dispensing a first underfill in a space defined between opposing faces of the chip and the laminate and dispensing a second underfill at least at a portion of an edge of the chip, the second underfill including a high aspect ratio material.

Abstract: A fixture assembly and method of forming a chip assembly is provided. The fixture assembly includes a first plate having an opening sized to accommodate a chip mounted on a laminate. The fixture assembly further includes a second plate mated to the first plate by at least one mechanical fastening mechanism. The fixture assembly further includes a space defined by facing surfaces of the first plate and the second plate and confined by a raised stepped portion of at least one of the first plate and the second plate. The space is coincident with the opening. The space is sized and shaped such that the laminate is confined within the space and directly abuts the stepped portion and the facing surfaces of the first plate and the second plate to be confined in X, Y and Z directions.

Abstract: A method of fabricating a chip package is provided. The chip package includes a laminate, a chip and conductive elements interposed between the chip and the laminate by which signals are transmitted among the chip and the laminate. The method includes dispensing a first underfill in a space defined between opposing faces of the chip and the laminate and dispensing a second underfill at least at a portion of an edge of the chip, the second underfill including a high aspect ratio material.

Abstract: An apparatus, system, and method are disclosed for connecting an integrated circuit device to a substrate. A plurality of standard diameter pillars and three or more increased diameter pillars are disposed on an integrated circuit device. The increased diameter pillars have a diameter that is greater than the standard diameter pillars and a height that is similar to the standard diameter pillars. The standard diameter pillars and the increased diameter pillars form a pattern on the integrated circuit device that corresponds to contact pads on a substrate opposite the integrated circuit device. A first group of solder bumps is disposed between the standard diameter pillars and the contact pads. A second group of solder bumps is disposed between the increased diameter pillars and the contact pads. The second group of solder bumps has pre-connection heights that are greater than pre-connection heights of the first group of solder bumps.

Abstract: A method of fabricating a chip package is provided. The chip package includes a laminate, a chip and conductive elements interposed between the chip and the laminate by which signals are transmitted among the chip and the laminate. The method includes dispensing a first underfill in a space defined between opposing faces of the chip and the laminate and dispensing a second underfill at least at a portion of an edge of the chip, the second underfill including a high aspect ratio material.

Abstract: A process and structure for forming an optical subassembly in an integrated circuit, comprising: defining electrically conducting lines and bonding pads in a metallization layer on a substrate; depositing a passivation layer over the metallization layer; etching the passivation layer to remove the passivation layer from each of the bonding pads and a portion of the metallization layer associated with each of the bonding pads; diffusing Cr from the lines proximate said bonding pads to prevent solder wetting down lines; bonding an optical device to one of the bonding pads; and attaching the substrate to a carrier utilizing solder bond attachment.

Abstract: A structure and method for converting a standard ceramic carrier into a temporary chip attach carrier, wherein the device comprises a substrate, a plurality of metal vias interspersed in the substrate, a carrier layer further comprising a cavity dam with a plurality of holes filled with conductive adhesive. The process of forming the temporary chip attach carrier comprises applying a secondary layer further comprising a plurality of holes on a substrate, applying conductive adhesive in the holes, curing the adhesive, placing a chip containing C4 solder bumps onto the secondary layer, applying a force onto the chip, testing and burning-in the secondary layer, removing the force from the chip, separating the chip from the secondary layer, and then re-using the secondary layer.