Abstract: A cache memory system is enabled into one of a plurality of cache modes in a cache memory system in a computer. The cache memory system has a first controller and two cache memories, the cache memories are partitioned into quadrants with two quadrants in each cache memory. A cache mode detector in the first controller detects a mirror cache mode set for the cache memory system. An address enabler in the first controller enables access to first pair of quadrants, one quadrant in each cache memory, in response to detection of a mirror cache mode. A second controller follows the cache mode set by the cache mode detector and has an address enabler. The address enabler in the second controller enables access to both quadrants in one cache memory in a non-mirror cache mode, and enables the access to a second pair of quadrants, one quadrant in each cache memory, in response to detection of a mirror cache mode by said cache mode detector.

Abstract: A cache memory system in a computing system has a first cache module storing data, a second cache module storing data, and a controller writing data simultaneously to both the first and second cache modules. A second controller can be added to also write data simultaneously to both the first and second cache modules. In a single write cycle each controller requests access to both the first and second cache modules. Both cache modules send an acknowledgement of the cache request back to the controllers. Each controller in response to the acknowledgements from both of the cache modules simultaneously sends the same data to both cache modules. Both of the cache modules write the same data into cache in their respective cache modules.

Abstract: A distributor apparatus and its method of operation for interconnecting a node of a bus in a node-limited serial data bus computer network to a plurality of subnode devices. A transmission on the bus is distributed or routed through the distributor to each subnode device connected thereto. A transmission from a subnode device is coupled to the bus through the distributor after the distributor selects one transmitting subnode device in the event that there are more than one subnode devices transmitting or requesting to transmit. Selection of one transmitting subnode device is carried out by rotating priority arbitration that occurs during an idle timing interval or quiet slot such that bus timing parameters are obeyed.

Abstract: An address conversion unit for a multiprocessor system including a common memory, and in which at least one processor includes a private memory, with the private memory and common memory having separate and distinct memory spaces. The conversion unit converts addresses between private addresses that are used within the processor itself and addresses that are used to retrieve contents of locations in common memory.