Abstract: An RF clocked device can include a signal processor operable to receive an RF signal having an RF signal frequency and output a clock signal having a clock frequency based on the RF signal frequency. The RF clocked device can also include a clock operable to receive, and operate, using the clock signal. The clock can output at least one of a time and a date. In addition, a clock system can include an RF clocked device. The RF clocked device can include a signal processor operable to receive an RF signal having an RF signal frequency and output a clock signal having a clock frequency based on the RF signal frequency. The RF clocked device can also include a clock operable to receive, and operate, using the clock signal. The clock can output at least one of a time and a date. The clock system can also include a client device operable to receive timing information from the RF clocked device.

Abstract: An RF clocked device can include a signal processor operable to receive an RF signal having an RF signal frequency and output a clock signal having a clock frequency based on the RF signal frequency. The RF clocked device can also include a clock operable to receive, and operate, using the clock signal. The clock can output at least one of a time and a date. In addition, a clock system can include an RF clocked device. The RF clocked device can include a signal processor operable to receive an RF signal having an RF signal frequency and output a clock signal having a clock frequency based on the RF signal frequency. The RF clocked device can also include a clock operable to receive, and operate, using the clock signal. The clock can output at least one of a time and a date. The clock system can also include a client device operable to receive timing information from the RF clocked device.

Abstract: A system and method for detecting Trojans and other intermittent severe defects in a digital circuit design. A simulation of the digital circuit design results in a value change dump file, which is compiled to form a value change summary file containing counts of the numbers of value changes for the signals in the digital circuit design. A discriminative neural network analyzes the value change summary file to determine whether an intermittent severe defect is present. A corpus of digital circuit designs, with and without intermittent severe defects, is used to train the discriminative neural network. The training process may involve dimensionality reduction of the data, enlargement of the data set, and data compression using an autoencoder.

Abstract: A system and method for detecting Trojans and other intermittent severe defects in a digital circuit design. A simulation of the digital circuit design results in a value change dump file, which is compiled to form a value change summary file containing counts of the numbers of value changes for the signals in the digital circuit design. A discriminative neural network analyzes the value change summary file to determine whether an intermittent severe defect is present. A corpus of digital circuit designs, with and without intermittent severe defects, is used to train the discriminative neural network. The training process may involve dimensionality reduction of the data, enlargement of the data set, and data compression using an autoencoder.

Abstract: Generally discussed herein are systems, apparatuses, and methods for providing an accurate and stable time base. A device can include a voter to receive a plurality of time source values, determine a central time value, and determine which of the plurality of time source values are valid, a deviance checker to determine a deviance set, a discrete time selector to provide a selector identification identifying which of the time source values is selected, and a network interface to provide a time value based on the selected time source value.

Abstract: Generally described herein are methods and systems for enhanced tamper and malware resistant computer architectures. A system for enhanced tamper and malware resistance can include a harvardizer configured to receive comingled instructions and data and produce separated instructions and data. A data memory can be configured to receive the separated data. An instruction memory that is physically separate from the data memory can be configured to receive the separated instructions. The system can include one or more computer processors that can be configured to execute the separated instructions and data. The system can include one or more encryptors or decryptors to help thwart injection based attacks.

Abstract: This disclosure addresses systems and methods for the protection of proprietary information by monitoring operational watermarks of an apparatus. A monitoring device may receive logical or physical watermark data from a defended apparatus. Watermark data may include any operational or environmental variable related to the defended apparatus. The monitoring device may maintain a baseline profile for the defended apparatus that includes watermark data. During monitoring of the defended apparatus by the monitor device, changes in the watermark data may be analyzed to determine if the baseline should be dynamically updated, or if the change indicates an anomaly. Anomalies may indicate an attempt to tamper with the defended apparatus. In response to the change that indicates an anomaly, the monitoring device may scrub the contents of the defended apparatus. In an embodiment, the monitoring device may also scrub its own memory in response to an anomaly.

Abstract: Generally described herein are methods and systems for enhanced tamper and malware resistant computer architectures. A system for enhanced tamper and malware resistance can include a harvardizer configured to receive comingled instructions and data and produce separated instructions and data. A data memory can be configured to receive the separated data. An instruction memory that is physically separate from the data memory can be configured to receive the separated instructions. The system can include one or more computer processors that can be configured to execute the separated instructions and data. The system can include one or more encryptors or decryptors to help thwart injection based attacks.

Abstract: This disclosure addresses systems and methods for the protection of proprietary information by monitoring operational watermarks of an apparatus. A monitoring device may receive logical or physical watermark data from a defended apparatus. Watermark data may include any operational or environmental variable related to the defended apparatus. The monitoring device may maintain a baseline profile for the defended apparatus that includes watermark data. During monitoring of the defended apparatus by the monitor device, changes in the watermark data may be analyzed to determine if the baseline should be dynamically updated, or if the change indicates an anomaly. Anomalies may indicate an attempt to tamper with the defended apparatus. In response to the change that indicates an anomaly, the monitoring device may scrub the contents of the defended apparatus. In an embodiment, the monitoring device may also scrub its own memory in response to an anomaly.

Abstract: A method for synchronizing nodes in a network is described that utilizes an interactive convergence technique. The technique utilizes communications protocol IEEE 1394 to broadcast each node's clock value to the other nodes in the network. Each node applies a voting algorithm to the set of broadcasted clock values to determine a voted clock value and each node's clock is set to that voted clock value. When a node's clock value is close in value to another node, those nodes are considered to be synchronized. The set of clock values to be used to determine the voted clock value consists of those nodes that are synchronized. The technique is implemented on hardware separate from the node's hardware and can be implemented on a field programmable gate array.

Abstract: A stand alone Redundancy Management System (RMS) provides a cost-effective solution for managing redundant computer-based systems in order to achieve ultra-high system reliability, safety, fault tolerance, and mission success rate. The RMS includes a Cross Channel Data Link (CCDL) module and a Fault Tolerant Executive (FE) module. The CCDL module provides data communication for all channels, while the FTE module performs system functions such as synchronization, data voting, fault and error detection, isolation and recovery. System fault tolerance is achieved by detecting and masking erroneous data through data voting, and system integrity is ensured by a dynamically reconfigurable architecture that is capable of excluding faulty nodes from the system and re-admitting healthy nodes back into the system.