Abstract: A building system including one or more memory devices configured to store instructions that, when executed on one or more processors, cause the one or more processors to collect building device data of a building device, generate a time correlated data stream for a data point, and generate a time correlated reliability data stream for the data point. The building device data includes a plurality of data samples of the data point. The time correlated data stream includes values of the plurality of data samples of the data point. The time correlated reliability data stream includes a plurality of reliability values time correlated to corresponding values of the plurality of data samples of the data point and indicating reliability of the values of the plurality of data samples of the data point.

Abstract: An electronic device can include a housing defining an aperture and a display positioned in the aperture. The display and the housing can define an internal volume in which a speaker assembly is positioned. The speaker assembly can include a speaker module and a speaker enclosure in fluid communication, with the speaker enclosure at least partially defining a speaker volume.

Abstract: A building system including one or more memory devices configured to store instructions that, when executed on one or more processors, cause the one or more processors to collect building device data of a building device, the building device data comprising a plurality of data samples of a data point and generate a time correlated data stream for the data point, the time correlated data stream comprising values of the plurality of data samples of the data point. The instructions cause the one or more processors to generate a time correlated reliability data stream for the data point, the time correlated reliability data stream comprising a plurality of reliability values indicating reliability of the values of the plurality of data samples of the data point.

Abstract: There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.

Abstract: There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.

Abstract: There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.

Abstract: There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.

Abstract: A device comprising: a substrate; a transmit antenna fabricated on the substrate and configured to transmit radio-frequency (RF) signals; a receive antenna fabricated on the substrate and configured to receive RF signals; and circuitry, disposed on the substrate and differentially coupled to the transmit and receive antennas, and configured to provide to the transmit antenna RF signals to be transmitted by the transmit antenna and to process RF signals received by the receive antenna, wherein the substrate comprises material for reducing harmonic coupling between the transmit antenna and the receive antenna.

Abstract: There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.

Abstract: There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive levels is planarized by chemical mechanical polishing.

Abstract: There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive levels is planarized by chemical mechanical polishing.

Abstract: A three-dimensional memory is provided that includes a first memory level and a second memory level monolithically formed above the first memory level. The first memory level includes a first steering element coupled in series with and vertically stacked above or below a first non-volatile state change element. The second memory level includes a second steering element coupled in series with and vertically stacked above or below a second non-volatile state change element. Other aspects are also provided.

Abstract: There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.

Abstract: An electronic component test device capable of testing electronic components in a plurality of test configurations. The device includes a probe head for providing a plurality of probe contact structures to an electronic component to be tested. The device includes an interconnect board coupled to the probe head. The interconnect board includes a plurality of conductive terminals, each of a first subset of the plurality of conductive terminals is coupled to one of a group of electrical signal lines for coupling to different types of external signals. The interconnect board includes a plurality of conductive lines. Each conductive line is coupled between a corresponding one of a plurality of conductive terminals in a second subset of the plurality of conductive terminals and a terminal for coupling to one of the plurality of probe contact structures.

Abstract: There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.

Abstract: There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.

Abstract: A pillar-shaped memory cell is provided that includes a steering element, and a non-volatile state change element coupled in series with the steering element. Other aspects are also provided.

Abstract: There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.

Abstract: There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.

Abstract: A three-dimensional memory is provided that includes a first memory level and a second memory level monolithically formed above the first memory level. The first memory level includes a first steering element coupled in series with and vertically stacked above or below a first non-volatile state change element. The second memory level includes a second steering element coupled in series with and vertically stacked above or below a second non-volatile state change element. Other aspects are also provided.