Patents by Inventor Thomas H. White
Thomas H. White has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11968001Abstract: A method of reducing transmission power for an encoded data stream includes the steps of receiving an incoming data stream having equal probability for a plurality of incoming data bits, assigning a symbol scheme to the received data bits of the incoming data stream according to probabilities of occurrence of individual ones of the received data bits, and transmitting an outgoing data stream according to the assigned symbol scheme having a second average transmit power, different than the first average transmit power, for a plurality of outgoing symbols.Type: GrantFiled: February 27, 2023Date of Patent: April 23, 2024Assignee: Cable Television Laboratories, Inc.Inventors: Thomas H. Williams, Gregory Charles White
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Patent number: 10043716Abstract: Embodiments of N-well or P-well strap structures are disclosed with lower space requirements achieved by forming the strap on both sides of one or more floating polysilicon gate fingers.Type: GrantFiled: August 22, 2016Date of Patent: August 7, 2018Assignee: Altera CorporationInventors: Dustin Do, Andy L. Lee, Giles V. Powell, Bradley Jensen, Swee Aun Lau, Wuu-Cherng Lin, Thomas H. White
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Publication number: 20160358825Abstract: Embodiments of N-well or P-well strap structures are disclosed with lower space requirements achieved by forming the strap on both sides of one or more floating polysilicon gate fingers.Type: ApplicationFiled: August 22, 2016Publication date: December 8, 2016Applicant: Altera CorporationInventors: Dustin Do, Andy L. Lee, Giles V. Powell, Bradley Jensen, Swee Aun Lau, Wuu-Cherng Lin, Thomas H. White
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Patent number: 9449962Abstract: Embodiments of N-well or P-well strap structures are disclosed with lower requirements achieved by forming the strap on both sides of one or more floating polysilicon gate fingers.Type: GrantFiled: August 4, 2011Date of Patent: September 20, 2016Assignee: Altera CorporationInventors: Dustin Do, Andy L. Lee, Giles V. Powell, Bradley Jensen, Swee Aun Lau, Wuu-Cherng Lin, Thomas H. White
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Patent number: 9270274Abstract: Circuits, methods, and apparatus that provide for protection of configuration bitstreams from theft. One exemplary embodiment receives a scrambled configuration bitstream with an integrated circuit. The scrambled configuration bitstream is descrambled using a plurality of multiplexers under control of a security key. A configuration bitstream is received in portions. One specific embodiment uses a key stored in memory to control a bank of multiplexers that descramble each of the received portions of the configuration bitstream. Other embodiments store longer keys, and use portions of the keys to descramble one or more portions of their respective configuration bitstreams. The outputs of the multiplexers are then stored in configuration memory cells.Type: GrantFiled: January 6, 2014Date of Patent: February 23, 2016Assignee: Altera CorporationInventors: Dirk Reese, Thomas H. White
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Patent number: 9087169Abstract: An integrated circuit fabricated by a mask set including a mask to generate a metal pattern defined by CAD software, the metal pattern generation method including: reading a binary data set, the data points in the set uniquely matched to a plurality of fixed metal tabs; and selecting a metal tab from a first set of selectable metal tabs for a first data value, or a second set of selectable metal tabs for a second data value for each of the fixed metal tabs; wherein a first set metal tab and a second set metal tab couples each said fixed metal tab to first and second voltages respectively.Type: GrantFiled: July 23, 2012Date of Patent: July 21, 2015Inventors: Raminda U. Madurawe, Thomas H. White
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Patent number: 8650409Abstract: Circuits, methods, and apparatus that provide for protection of configuration bitstreams from theft. One exemplary embodiment receives a scrambled configuration bitstream with an integrated circuit. The scrambled configuration bitstream is descrambled using a plurality of multiplexers under control of a security key. A configuration bitstream is received in portions. One specific embodiment uses a key stored in memory to control a bank of multiplexers that descramble each of the received portions of the configuration bitstream. Other embodiments store longer keys, and use portions of the keys to descramble one or more portions of their respective configuration bitstreams. The outputs of the multiplexers are then stored in configuration memory cells.Type: GrantFiled: September 15, 2004Date of Patent: February 11, 2014Assignee: Altera CorporationInventors: Dirk Reese, Thomas H. White
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Patent number: 8432724Abstract: Integrated circuits with memory cells are provided. A memory cell may have four inverter-like circuits connected in a ring configuration and four corresponding storage nodes. The four inverter-like circuits may form a storage portion of the memory cell. Some of the inverter-like circuits may have tri-state transistors in pull-up and pull-down paths. The tri-state transistors may be controlled by address signals. Address and access transistors may be coupled between some of the storages nodes and a data line. The address and access transistors may be used to read and write into the memory cell. During write operations, the address signals may be asserted to turn off the tri-state transistors and eliminate contention current from the cell. During read and normal operations, the address signals may be deasserted to allow the inverter-like circuits to hold the current state of the cell while providing soft error upset immunity.Type: GrantFiled: April 2, 2010Date of Patent: April 30, 2013Assignee: Altera CorporationInventor: Thomas H. White
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Publication number: 20120261738Abstract: Embodiments of N-well or P-well strap structures are disclosed with lower space requirements achieved by forming the strap on both sides of one or more floating polysilicon gate fingers.Type: ApplicationFiled: June 29, 2012Publication date: October 18, 2012Inventors: Dustin Do, Andy Lee, Giles V. Powell, Bradley Jensen, Swee Aun Lau, Wuu-Cherng Lin, Thomas H. White
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Patent number: 8217464Abstract: Embodiments of N-well or P-well strap structures are disclosed with lower space requirements achieved by forming the strap on both sides of one or more floating polysilicon gate fingers.Type: GrantFiled: August 6, 2010Date of Patent: July 10, 2012Assignee: Altera CorporationInventors: Dustin Do, Andy L. Lee, Giles V. Powell, Bradley Jensen, Swee Aun Lau, Wuu-Cherng Lin, Thomas H. White
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Publication number: 20120032276Abstract: Embodiments of N-well or P-well strap structures are disclosed with lower space requirements achieved by forming the strap on both sides of one or more floating polysilicon gate fingers.Type: ApplicationFiled: August 6, 2010Publication date: February 9, 2012Applicant: Altera CorporationInventors: Dustin Do, Andy Lee, Giles V. Powell, Bradley Jensen, Swee Aun Lau, Wuu-Cherng Lin, Thomas H. White
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Publication number: 20110242880Abstract: Integrated circuits with memory cells are provided. A memory cell may have four inverter-like circuits connected in a ring configuration and four corresponding storage nodes. The four inverter-like circuits may form a storage portion of the memory cell. Some of the inverter-like circuits may have tri-state transistors in pull-up and pull-down paths. The tri-state transistors may be controlled by address signals. Address and access transistors may be coupled between some of the storages nodes and a data line. The address and access transistors may be used to read and write into the memory cell. During write operations, the address signals may be asserted to turn off the tri-state transistors and eliminate contention current from the cell. During read and normal operations, the address signals may be deasserted to allow the inverter-like circuits to hold the current state of the cell while providing soft error upset immunity.Type: ApplicationFiled: April 2, 2010Publication date: October 6, 2011Inventor: Thomas H. White
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Patent number: 7797033Abstract: The present invention broadly provides an improved ingestible capsule (28) that is arranged to sense one or more physiological parameters within a mammalian body, an to transmit such parameters to an extra-corporeal receiver (50). In use, the capsule and receiver perform the method of determining the real-time location of the capsule within a tract of a mammal. This method includes the steps of providing the capsule, the capsule having one or more sensors, ingesting the capsule, transmitting a signal from the capsule, receiving the transmitted signal, and determining the real-time location of the capsule within the tract as a function of the received signal. The received signal may also indicate the value of one or more sensed parameters.Type: GrantFiled: March 24, 2003Date of Patent: September 14, 2010Assignee: Smart Pill CorporationInventors: David T. D'Andrea, John R. Semler, Thomas H. White
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Patent number: 7710147Abstract: Techniques and circuitry provide fast, accurate, proper, and reliable transfer of configuration data from an on-chip nonvolatile memory to the programmable logic core of a programmable logic integrated circuit. A first technique includes not allowing the programmable logic to be configured until the data held in the on-chip nonvolatile memory can be read correctly and reliably. A second technique includes verifying the configuration data is transferred from the nonvolatile memory to the programmable logic core correctly and without error during the transfer process. These two techniques may be combined or used individually during the configuration of an integrated circuit.Type: GrantFiled: May 19, 2008Date of Patent: May 4, 2010Assignee: Altera CorporationInventors: Thomas H. White, William Bradley Vest, Dirk Alan Reese, Myron Wai Wong
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Patent number: 7550994Abstract: A programmable logic integrated circuit has user-accessible nonvolatile memory for use by the programmable logic. In a specific embodiment, the programmable logic integrated circuit has a programmable logic array portion and a nonvolatile memory array portion. The nonvolatile memory array portion is segregated into a boot data part and a user data partition. The boot data partition holds data for configuring the programmable logic portion on power up, and the user data partition is for use by the programmable logic. A user can store and retrieve data from the user data partition. A built-in oscillator can be programmably connected from the nonvolatile memory portion to the PLD portion.Type: GrantFiled: January 29, 2007Date of Patent: June 23, 2009Assignee: Altera CorporationInventors: Rafael C. Camarota, Thomas H. White
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Publication number: 20090128189Abstract: In a first aspect, a three dimensional programmable logic device (PLD) comprises a plurality of distributed programmable elements located in a substrate region; and a contiguous array of configuration memory cells, a plurality of said memory cells coupled to the plurality of programmable elements to configure the programmable elements, wherein: the memory array is positioned substantially above or below the substrate region; and the memory array and the substrate region layout geometries are substantially similar. In a second aspect, the 3D PLD comprises a contiguous array of metal cells, each metal cell having the configuration memory cell dimensions and a metal stub coupled to a said configuration memory cell and to one or more of said programmable elements.Type: ApplicationFiled: November 19, 2007Publication date: May 21, 2009Inventors: Raminda Udaya Madurawe, Thomas H. White
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Patent number: 7375551Abstract: Techniques and circuitry provide fast, accurate, proper, and reliable transfer of configuration data from an on-chip nonvolatile memory to the programmable logic core of a programmable logic integrated circuit. A first technique includes not allowing the programmable logic to be configured until the data held in the on-chip nonvolatile memory can be read correctly and reliably. A second technique includes verifying the configuration data is transferred from the nonvolatile memory to the programmable logic core correctly and without error during the transfer process. These two techniques may be combined or used individually during the configuration of an integrated circuit.Type: GrantFiled: January 18, 2006Date of Patent: May 20, 2008Assignee: Altera CorporationInventors: Thomas H. White, William Bradley Vest, Dirk Alan Reese, Myron Wong
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Patent number: 7345509Abstract: Integrated circuit devices are provided that include power detection circuits that indicate whether power supplies have reached functional voltage levels. The power detection circuits include latches coupled to power supplies that can detect whether all the power supplies have reached functional voltage levels, logic circuits to provide appropriate output signals, and well bias circuits that supply current to the power detection circuits. Well bias circuits provide current from first power supplies to reach functional voltage levels so that indication may be provided from the power detection circuit without requiring functional voltage levels of all power supplies. Outputs from power detection circuits can be combined with control signals, for various applications. Applications include holding an integrated circuit device in reset until power supplies have reached functional voltage levels.Type: GrantFiled: July 29, 2005Date of Patent: March 18, 2008Assignee: Altera CorporationInventors: Sergey Y Shumarayev, Thomas H White
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Patent number: 7307446Abstract: Programmable logic device integrated circuitry having differential I/O circuitry is provided. The differential I/O circuitry may include output drivers for providing differential digital output data signals across pairs of output lines. A user may program the I/O circuitry to accommodate different high-speed differential I/O signaling standards. The user may also program the I/O circuitry to provide a desired amount of preemphasis to the output data signals.Type: GrantFiled: August 24, 2006Date of Patent: December 11, 2007Assignee: Altera CorporationInventors: Sergey Y. Shumarayev, Thomas H. White, Rakesh H. Patel, Wilson Wong
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Patent number: 7119579Abstract: A supply voltage detection circuit determines when the voltage for any one of the power supply signals received by an integrated circuit device is below its steady state level, as may occur during a hot socket condition when the device is inserted in or removed from a powered-on system. A first detection circuit determines when the first supply voltage level is below its steady state level, and a second detection circuit determines when the second supply voltage level is below its steady state level. A logic circuit provides a detected condition signal that disables current flow through an input/output terminal associated with the supply voltage detection circuit. The circuit is able to rapidly detect hot socket conditions for a wide range of power supply signal levels, including low supply signal levels, while limiting leakage current effects.Type: GrantFiled: December 6, 2004Date of Patent: October 10, 2006Assignee: Altera CorporationInventors: Yan Chong, Chiakang Sung, Bonnie Wang, Khai Nguyen, Joseph Huang, Xiaobao Wang, Philip Pan, In Whan Kim, Gopi Rangan, Tzung-Chin Chang, Surgey Y. Shumarayev, Thomas H. White